RISC-V Summit: join us for Antmicro’s keynote, talk, tutorials, live demos and more
The inaugural RISC-V Summit is only a week away, promising to put practical implementations in real products and open tooling into the spotlight. The ecosystem is maturing, and we may expect a series of exciting announcements by RISC-V leaders, Antmicro included. We are thrilled to be spearheading RISC-V’s next big steps into the mainstream, and the Summit will surely be a manifest of the emerging culture of open standards and collaborative innovation that we hold to be inevitable.
This new age of open methodologies and tooling is paving the way to a less constrained, less vendor-locked and faster-evolving reality where we see Antmicro’s unique role. Join us on Tuesday, December 5th for Michael Gielda’s keynote address “Accelerating Innovation: Why Google’s TPU Was Just the Start” - discussing some exciting developments in open digital design, FPGA implementations, open source IP, tools, and edge AI on RISC-V that Antmicro is making happen.
RISC-V Hackathon and open source Linux-enabled soft SoC
Another activity which gets us excited for the Summit is the two-day RISC-V Hackathon organized on December 4th and 5th by Western Digital, who is also co-sponsoring our design efforts that will be the foundation of the Hackathon - a Linux-enabled open source RISC-V SoC based on LiteX! This effort, to be released as open source (of course) will enable Linux developers to build software for RISC-V on a low-cost board from Future Electronics - the Avalanche board with an on-board Microsemi PolarFire FPGA.
Renode and pre-silicon development of Linux-capable RISC-V SoC
As is customary, we will also be presenting a Renode talk related to our open source Renode simulation framework, this time announcing the support of a new major Linux-enabled RISC-V SoC from our RISC-V Foundation partner, with Renode being the primary enabler for pre-silicon development. The exciting hardware/software co-design capabilities of Renode, exemplified earlier by our collaboration with Dover Microsystems will now be taken to the next level. On Tuesday, December 5th, join in for “Making a Complex, Linux-enabled SoC Available to Everyone Today with Renode” where we will explain how Antmicro managed to deliver the first-ever mainstream Linux-enabled RISC-V SoC platform into the hands of developers worldwide without limitations using the free and open source Renode framework.
Zephyr and Linux tutorials
We will also be giving two practical hands-on tutorials related to Antmicro’s recent work in bringing forth the official RISC-V Getting Started Guide for early developers on the inaugural day of the Summit, December 3rd.
The first tutorial, “Running a Linux-Capable Open Source Soft SoC on the Avalanche Board with MicroSemi PolarFire FPGA”, led by Antmicro in collaboration with Western Digital and Microchip, will showcase a the aforementioned Linux-enabled open source SoC in a Microsemi PolarFire FPGA that can serve as an entry point to open source digital design in the broader sense.
In the second tutorial, tohgether with Google we’re addressing those interested in RISC-V for resource-constrained AI applications. “Running the Zephyr RTOS and Machine Learning with TensorFlow Lite on RISC-V” will tell about the status of Zephyr and TF Lite, plans for TF Lite RISC-V support, developing with Zephyr and TF Lite on real hardware and testing in Renode, which is a recommended tool both by Zephyr and TF Lite.
RISC-V Contest resolution - and Antmicro’s booth!
The RISC-V Summit will also see the resolution of the SoftCPU design contest sponsored by Google, Antmicro, Microsemi and Lattice, which had its participants implement a RISC-V FPGA core capable of running the Zephyr OS which is quickly becoming a standard in the ecosystem.
We see a growing number of customers wanting to leverage the open nature of RISC-V and adopt a new, more software-driven workflow. Meet us in person showcasing our RISC-V services and tools for early adopters at Antmicro’s booth, and a dedicated Renode demo at Microchip’s booth (Expo Hall open Tuesday from 10:00 am to 7:00 pm, Wednesday from 10:00 to 3:30 pm).
By being a Diamond Sponsor for the first global RISC-V Summit and leading this series of developer-oriented activities, we hope to spark even more creative energy in the rapidly broadening RISC-V ecosystem and encourage industry partners already navigating towards open standards to take their next big step with Antmicro. If you see the future as more open-source and software-driven than ever before, get in touch with us at email@example.com - we’ll be happy to arrange a meeting!