Tagged as:

fpga

MAIN BLOG
OPEN HARDWARE

OPEN SOURCE SYSTEM ON MODULE WITH MICROCHIP POLARFIRE SOC

Published:

Photo of the PolarFire SoM The PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks to the ongoing collaboration...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INITIAL ASSERTION CONTROL SUPPORT IN VERILATOR

Published:

Initial assertion control support in Verilator Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INTRODUCING CONSTRAINED RANDOMIZATION IN VERILATOR

Published:

Constrained randomization in Verilator illustration Large and complex SystemVerilog designs, such as CPUs, are difficult to test thoroughly, as there are many interesting signal combinations that influence a design’s behavior, including corner cases that are easy to overlook...
OPEN SOURCE TOOLS, OPEN ISA

DEVELOPING AND TESTING HETEROGENEOUS SPACE SYSTEMS WITH RENODE

Published:

Renode for space - main illustration While landing humans on the Moon was a feat accomplished with very basic compute power of 2MHz provided by the Apollo Guidance Computer, modern spacecraft can take advantage of a much more advanced and capable data processing...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

ADDING PHYSICAL MEMORY PROTECTION TO THE VEER EL2 RISC-V CORE

Published:

PMP for VeeR EL2 - graphical interpretation Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code...
OLDER
CLOSE 

TAGS

4k ai allied-vision ambiq android arm arm-renode asic asic-tools autosar bluetooth bsp build-systems cfu chips-alliance chisel cloud co-simulation cocotb computer-vision containers coral cortex-a cortex-m cortex-r ddr deep-learning dma edge-ai edgetpu embedded-world enclustra events f4pga fpga fpga-tools framos fusesoc gdb google gui hifive i-mx7 i-mx8 intel iot jetson jetson-nano jetson-orin jetson-tk1 jetson-tx1 jetson-tx2 jetson-xavier kenning lattice leon linux litex machine-learning markdown mcu meta microchip migen mipi-csi-2 movidius networking nordic nuvoton nvidia nxp object-detection open-hardware open-titan openembedded openlane openroad ota partners picorv polarfire polarfire-soc press-release protoplaster python quicklogic rdfm reapi renode risc-v riscv rocket ros rust scalerunner sel4 sifive simulation singularity skywater snapdragon soc spinalhdl stm svevn systemc systemverilog tegra tensorflow toradex tracking triple-modular-redundancy tsn ultrascale v4l2 verification verilator verilog vexriscv video-processing visual-system-designer webassembly xilinx xtensa zephyr zynq
AREAS
Robotics & Drones
Industry & Trans­porta­tion
Security & Access Control
Lab & Measure­ment
Defense & Aero­space
TECHNOLOGIES
FPGA
Hetero­geneous CPU/GPU systems
RISC-V
Internet of Things
Human-Machine Inter­faces
Vision Systems
SERVICES
Soft­ware & BSPs
Cloud
Product Develop­ment
Hard­ware Design
Edge AI
PLATFORMS
Open Source Jetson Baseboard
Apalis Baseboard
TX2 Deep Learning Platform
Ultra­Scale+ Pro­cess­ing Module
Custom Camera Platforms
Memory testing platforms
DC-SCM-compatible open source BMC
Industrial Android
Renode
Kenning
ANTMICRO
Contact
Partners
Resources
The Company
Careers
Blog