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OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INTRODUCING CONSTRAINED RANDOMIZATION IN VERILATOR

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Constrained randomization in Verilator illustration Large and complex SystemVerilog designs, such as CPUs, are difficult to test thoroughly, as there are many interesting signal combinations that influence a design’s behavior, including corner cases that are easy to overlook...
OPEN SOURCE TOOLS, OPEN ISA

DEVELOPING AND TESTING HETEROGENEOUS SPACE SYSTEMS WITH RENODE

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Renode for space - main illustration While landing humans on the Moon was a feat accomplished with very basic compute power of 2MHz provided by the Apollo Guidance Computer, modern spacecraft can take advantage of a much more advanced and capable data processing...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

ADDING PHYSICAL MEMORY PROTECTION TO THE VEER EL2 RISC-V CORE

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PMP for VeeR EL2 - graphical interpretation Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code...
OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN FPGA

INITIAL SUPPORT FOR ARMV7-R CPUS IN RENODE WITH CORTEX-R5 AND CORTEX-R8

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Initial support for Cortex-R5 and Cortex-R8 in Renode Following the announcement of support for ARMv8-A and ARMv8-R ISAs earlier this year, Antmicro has now extended its Renode system simulation framework with initial support for Cortex-R5 and Cortex-R8 cores implementing the...
OPEN SOURCE TOOLS, OPEN ASICS

INITIAL OPEN SOURCE SUPPORT FOR UVM TESTBENCHES IN VERILATOR

Published:

Running simple UVM testbenches in Verilator Leading the efforts of the Tools Workgroup in CHIPS Alliance, across a variety of customer projects, as well as own R&D, at Antmicro we are actively looking for and capturing the productivity enhancements that can be achieved...
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