OPEN FPGA, OPEN ASICS, OPEN ISA, OPEN SOURCE TOOLS
ENABLING OPEN SOURCE IBEX SYNTHESIS AND SIMULATION IN VERILATOR/YOSYS VIA UHDM/SURELOG
Published:
Throughout 2020 we have been hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe...
Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as...
