Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of...
Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
Antmicro has created a broad portfolio of open source hardware designs that constitute a perfect entry point for product development, as showcased on our Open Hardware Portal. Since a lot of our projects focus on complex applications...
Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
Antmicro’s typical industrial customer would work with us to create advanced devices based on high-end processing platforms - and the baseboards, adapters and bridges showcased on our Open Hardware Portal are a great starting...
Large and complex SystemVerilog designs, such as CPUs, are difficult to test thoroughly, as there are many interesting signal combinations that influence a design’s behavior, including corner cases that are easy to overlook...
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