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verification

OPEN SOURCE TOOLS

SUPPORT FOR UPSTREAM UVM 2017 IN VERILATOR

Published:

Upstream UVM support in Verilator Universal Verification Methodology (UVM) is one of the most popular verification methods in digital design, focusing on standardization and reusability of verification IP and environments. For the last few years, Antmicro has...
OPEN HARDWARE, OPEN SIMULATION, OPEN SOURCE TOOLS

OPEN SOURCE THERMAL SIMULATION AND ANALYSIS WITH 3D VISUALIZATIONS

Published:

Temperature measuring setup Thermal simulation and analysis is an invaluable tool in hardware design and integration, providing critical information about thermal performance of a device (such as temperature distribution across electrical and mechanical...
OPEN ASICS, OPEN FPGA, OPEN SOFTWARE LIBRARIES

ENABLING OPEN SOURCE UVM VERIFICATION OF AXI-BASED SYSTEMS IN VERILATOR

Published:

Open source UVM verification of AXI systems in Verilator Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of...
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