Open Instruction Set Architecture

RISC-V (pronounced “risk-five”) is an instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

RISC-V logo

With its strong tooling support, growing ecosystem as well as very low barriers of adoption, RISC-V is very well positioned to replace many of the non-standard, proprietary cores still present in the industry today, allowing companies to offload the cost of developing and supporting custom toolchains and isolated ecosystems by utilizing an open standard.

Antmicro is a Platinum Founding member of the RISC-V Foundation as a natural consequence of our previous activity in open source and open hardware movements and our work encompassing embedded software, FPGA and hardware. We are strengthening the software ecosystem of RISC-V by e.g. maintaining the RISC-V port of the Zephyr RTOS, and actively participating in the marketing efforts of the Foundation to increase the awareness of RISC-V and its adoption in early applications, such as the AXIOM Gamma 4K camera or the RISC-V badge.

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