Antmicro’s TX2 platform released as open hardware

Multi-core VexRiscv in Litex

Microwatt and the POWER ISA support in Renode

Updated Jetson Nano/Xavier NX open source baseboard

SystemVerilog linting and formatting in FuseSoC

Open source hardware dual camera module for stereovision

Open hardware FPGA video platform

High-speed stereo camera for industrial use cases

CivetWeb in Zephyr

Single Object Tracking for ROS

SDI/HDMI to HDMI/MIPI smart converter/streamer

Speeding up builds with Remote Execution API

Open source Alvium drivers for TX2 (and Nano)

Renode support for QuickLogic EOS S3 SoC

Antmicro and zGlue release rapid turnaround chiplet-based GEM ASIC

TFLite in Zephyr

Open USB test suite

Antmicro exhibits at RISC-V Summit 2019

Open SystemVerilog Test Suite

Jetson Xavier™ NX with Antmicro's Open Source Jetson baseboard

EtherBone support in Renode

pyvidctrl tool for managing camera settings

Singularity at Antmicro

Time Sensitive Networking in Zephyr

Renode 1.8: EtherBone co-simulation, more RISC-V platforms

Updated Jetson Nano Baseboard + ALVIUM cameras

FastVDMA: an open DMA controller by Antmicro

Renode + Verilator HDL co-simulation

Zephyr on Zynq UltraScale+ Cortex-R5

Multi-core debugging with GDB in Renode

Automated cloud builds for edge AI devices

Verilog simulation with Cocotb and Verilator

Get Started with Zephyr on RISC-V

Renode 1.7 with Microchip SAME70, TSN, Verilator co-simulation

Open Jetson Nano AI board gets Data Modul HMI

Antmicro's open Android BSP for Apalis TK1

Security IP HW/SW co-design with RISC-V and Renode

Open hardware Google Coral baseboard

Open hardware NVIDIA Jetson nano baseboard

Open digital design

Renode 1.6 with RISC-V PolarFire FPGA SoC

Jetson Xavier + Antmicro AI + Allied Vision cameras

i.MX8 + Movidius AI accelerator

Open Triple Modular Redundancy demonstrator with Zephyr on UltraScale+