Single Object Tracking for ROS

SDI/HDMI to HDMI/MIPI smart converter/streamer

Speeding up builds with Remote Execution API

Open source Alvium drivers for TX2 (and Nano)

Antmicro exhibits at RISC-V Summit 2019: Renode, Fomu and open chip design

Renode support for QuickLogic EOS S3 SoC

Tensorflow Lite in Zephyr on LiteX/VexRiscv

Open USB test suite

Open SystemVerilog Test Suite

Jetson Xavier NX with Antmicro's Open Source Jetson baseboard

EtherBone support in Renode

pyvidctrl: text-based tool for managing camera settings

Portable containers with Singularity

Time Sensitive Networking in Zephyr

Renode 1.8: EtherBone co-simulation, more RISC-V platforms

Updated Jetson Nano Baseboard + Alvium cameras

FastVDMA: an open DMA controller by Antmicro

Renode + Verilator HDL co‑simulation

Zephyr on Zynq UltraScale+ Cortex-R5

Multi-core debugging with GDB in Renode

Automated cloud builds for edge AI devices

Get Started with Zephyr on RISC-V

Open source Verilog simulation with Cocotb and Verilator

Antmicro's open Android BSP for Apalis TK1

Renode 1.7 with Microchip SAM E70, TSN, Verilator co-simulation

i.MX8 + Movidius AI accelerator

Open Jetson Nano AI board gets Data Modul HMI

Security IP HW/SW co-design with RISC-V and Renode

Open hardware Google Coral baseboard

Open digital design

Open hardware NVIDIA Jetson nano baseboard

Renode 1.6 with RISC-V PolarFire FPGA SoC

Jetson Xavier + Antmicro AI + Allied Vision cameras

Open Triple Modular Redundancy demonstrator with Zephyr on UltraScale+