Renode 1.2 with RISC-V support to be presented at 7th RISC-V Workshop
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Building on the great momentum behind Antmicro’s open source multinode simulation framework, and in preparation for the 7th RISC-V Workshop happening in Milpitas, CA this week, Antmicro has just announced the release of Renode 1.2 - a landmark moment for the project that introduces official support for the acclaimed RISC-V architecture.
Microsemi’s contribution
At Antmicro we truly believe that the open, flexible, extendible and modular RISC-V ISA is a revolution the world has been waiting for, and as both a Founding Member of the organization that drives it and a service company helping early adopters maximize the benefit of using RISC-V, we happily welcomed Microsemi’s sponsorship of the effort towards supporting their RISC-V based Mi-V platform in Renode. Mi-V support is included in release 1.2, which also adds the integration with Microsemi’s SoftConsole IDE.
Microsemi, themselves a Founding Member of the Foundation and one of the key players in the ecosystem, has also co-sponsored first-class Windows support, released in Renode version 1.1 earlier this month, in order to enable Mi-V users develop their RISC-V based designs on the host platform of their choice.
The synergy between Renode and RISC-V
Renode and RISC-V are a natural match: both technologies are software-driven, open, modular, flexible and encouraging reuse. Renode provides the ability to model entire SoCs, assembling them from reusable building blocks, which very well corresponds with the paradigm shift towards customized silicon development brought about by RISC-V. This important commonality, connected with how easy it is to extend and integrate Renode with both well-known and new tooling, and the fact that the framework, just like RISC-V, is meant to enable more trasparent, better tested (also in terms of security) and more configurable systems, make Renode and RISC-V a perfect match.
Renode at the 7th RISC-V Workshop
To learn more about how Antmicro can help you to adopt a software, test-driven approach to RISC-V development and harvest the synergies from using Renode to simulate RISC-V SoCs, don’t miss our presentation during the RISC-V Simulation Infrastructure panel at the upcoming 7th RISC-V Workshop at Western Digital: “Renode: a flexible, open-source simulation framework for building scalable, well-tested RISC-V systems”.
Other developments
Building on the recent work with the RIOT OS team, the ability to test firmware for a number of other platforms supported in Renode, like the EFM32MG which powers e.g. IKEA TRÅDFRI, has been proposed. This is an exciting development and will definitely increase the potential for using RIOT and Renode together.
Besides RISC-V, release 1.2 includes some smaller but important changes, like adding a thin OpenOCD layer in GDB remote protocol support, adjusting timers to enable holding values up to 64 bits and some bugfixing of issues reported in the previous release.
See the full changelog in the Renode GitHub repository.
