OPEN SIMULATION, OPEN SOURCE TOOLS
OPEN SIMULATION, OPEN SOURCE TOOLS

TRACE-BASED EVALUATION OF CPU CACHE USAGE IN RENODE

Published:

Trace-based evaluation of CPU cache usage in Renode illustration

Although cache modeling is usually not part of ISS level simulation, there are cases where it’s crucial to understand memory access patterns e.g., when building a new chip and deciding on cache size and layout, or working on low-level, time-critical firmware...

OPEN ISA, OPEN SIMULATION
OPEN ISA, OPEN SIMULATION

INTRODUCING FAST RISC-V INTERRUPTS SUPPORT IN RENODE FOR REAL TIME APPLICATIONS

Published:

Fast RISC-V interrupts support in Renode illustration

Real time applications such as space or automotive where instant autonomous decision making is crucial require configurable standardized interrupt controllers. There are many well-known examples such as the Global Interrupt Controller (GIC) for Cortex-A...

OPEN ASICS, OPEN FPGA, OPEN SOFTWARE LIBRARIES
OPEN ASICS, OPEN FPGA, OPEN SOFTWARE LIBRARIES

ENABLING OPEN SOURCE UVM VERIFICATION OF AXI-BASED SYSTEMS IN VERILATOR

Published:

Open source UVM verification of AXI systems in Verilator

Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of nearly every imaginable feature...

OPEN SIMULATION, OPEN SOURCE TOOLS
OPEN SIMULATION, OPEN SOURCE TOOLS

TESTING COMPLEX, HETEROGENEOUS AMP SYSTEMS WITH RENODE USING ZYNQ ULTRASCALE+

Published:

image text

Asymmetric multiprocessing (AMP) setups are very common in modern SoCs which mix various types of cores or even architectures to provide sufficient processing power when needed, while keeping the system energy efficient overall. The AMP architecture is...

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