Antmicro is happy to announce the next, 1.14 release of our open source Renode simulation framework, including lots of new developments originating from both customer and R&D projects, along with community contributions. Since the last release, we’ve passed...
Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The HDL source can...
Digital circuits are becoming more and more complicated due to constant technology development and increasing user expectations. In response to this growing complexity, development tools that provide a higher level of abstraction for digital system designers...
OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN FPGA, OPEN ASICS
Customers interested in building new industrial or consumer devices, typically involving one or more PCBs and based on Linux, Zephyr or Android (or even all of them at the same time), often approach Antmicro before they know what exact components they want...
Verilator can boast the status of one of the most widely used free and open source digital design tools for ASIC and FPGA development. To stay on top of the ever-increasing complexity of ASIC and FPGA devices, as users and contributors, Antmicro has been...
Bluetooth Low Energy (BLE) is one of the most popular wireless protocols used in consumer devices including blood pressure monitors, wearables, and smart home appliances. Renode, Antmicro’s embedded and IoT simulation framework, has supported the BLE protocol...