OPEN TOOLCHAIN, OPEN OS, OPEN AI, OPEN FPGA IP

TENSORFLOW LITE IN ZEPHYR ON LITEX/VEXRISCV

Published:

TensorFlow Lite and Zephyr logos

While much of the focus for the recent developments in AI has been on cloud-centric implementations, there are many use cases where AI algorithms have to be run on small and resource constrained devices. Google’s TensorFlow Lite, a smaller brother of one...

OPEN FPGA IP, OPEN TOOLCHAIN

TESTING OPEN SOURCE USB IP CORES WITH PYTHON AND COCOTB

Published:

USB testing diagram

USB is often a daunting topic for developers, and implementing support for it from scratch is a time consuming task. When the expected result is more complicated than a USB-to-serial bridge, the solution would be to either use a hardware transceiver or...

OPEN FPGA IP, OPEN TOOLCHAIN, OPEN ASICS

AN OPEN SOURCE SYSTEMVERILOG TEST SUITE

Published:

SystemVerilog logo

At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools.

Verilog, SystemVerilog and open tooling

For FPGA development flows...

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