Implementing automatic clock gating in the OpenROAD ASIC design toolchain

Reducing power usage is a major aspect of chip design, important especially for energy-efficient systems and battery-powered devices. A significant amount of the power used by a typical chip is consumed by gate switching, and sequential logic (i.e. logic driven by a clock) is a significant part of dynamic power dissipation, making it a prime candidate for optimization.

Clock gating is a technique for lowering power consumption in digital circuits by disabling clock signals to portions of the circuit when they are not in use. It is often done manually by hardware designers, and while it’s still an effective approach, as the designer may have deep knowledge about the circuit which is hard to replicate, it’s also costly and time-consuming. The alternative is automatic clock gating which allows for much faster iteration, especially for designs that are generated in a higher-level hardware description language - the clock gating process can be performed automatically on the final netlist whenever it’s regenerated from the high level description.

In a recent customer project we introduced automatic clock gating to the open source OpenROAD ASIC design toolchain. In the following paragraphs we will walk you through the process of implementing automatic clock gating, describe the new cgt module in OpenROAD and show how it allows us to reduce power usage, using the Ibex CPU as an example.

Automatic clock gating overview

When performing automatic clock gating, for any given register you need to first find candidate nets that could be included in the registers’ gating condition (a function that combines several wires/nets, that decides whether the registers should be enabled). The candidate nets have to be in some way related to the gated registers, as otherwise it’s impossible to reason about whether they could form a gating condition. This step is largely heuristics-based, and requires considering several factors, including timing constraints, proximity to the registers, and percentage of time a given signal is high (the lower the better).

Next, you need to construct a gating condition from the candidates. The simplest way to do it is to use the OR/AND logic gates. The set of nets that comprise a gating condition should be minimal (shouldn’t contain nets that don’t affect the result or cause the condition to be enabled more than needed). The final decision whether a gating condition is correct must be proven mathematically, e.g. by a SAT solver. To speed up this process, you can prune candidates by randomly simulating them first to quickly find counterexamples.

Implementing automatic clock gating in OpenROAD

The implementation is described in the GitHub Pull Request. It adds a new module, called cgt, to the OpenROAD toolchain. When invoked, this module gathers all registers in the design. For each register, using the BFS algorithm, it gathers all connected nets up to a user-configurable limit (by default 100). The limit is there to make this process faster, as gathering more nets empirically resulted in far worse execution time with no real quality improvements. When the module encounters a register, it doesn’t go through it; it stops and goes in different directions.

Next, the gathered network is exported to ABC, an open source logic synthesis tool widely adopted in the industry. ABC is used to check whether the network can form a correct gating condition. First, simulation with random stimuli quickly checks for counterexamples. Then, if no counterexample was found, a SAT solver is employed to prove that the gating condition is correct. If a set of all nets doesn’t form a correct gating condition, cgt moves on to the next register. Otherwise, it checks if after removing half of the nets, the gating condition still works. If so, it drops that half of the nets. Otherwise, it recurses into the other half of the nets to minimize that set. Then, it recurses into the first half of the nets.

This process produces a minimal set of nets that form a gating condition (not necessarily optimal). The minimal set of nets with the corresponding gated register is then added to a list of accepted gating conditions, provided that that the list doesn’t already contain it. If it does, the gated register is added to the list next to the pre-existing condition. Additionally, before checking a new gating condition, cgt checks if a previously accepted condition is suitable for the register. If so, it adds the register to the accepted list next to the pre-existing condition.

For each accepted gating condition, cgt inserts a new clock gate that gates the corresponding registers under the gating condition. If the number of registers that can be gated by the condition is lower than a certain user-configurable number (by default 10), it doesn’t insert the clock gate and moves on to the next accepted condition.

Usage

To use the automatic clock gating feature in OpenROAD, just load your design and run clock_gating:

read_liberty path/to/pdk/cell/library.lib
read_db path/to/your/design.odb
read_sdc path/to/your/constraints.sdc

clock_gating

In a recent article we described an open source-driven flow for power analysis with Verilator and OpenROAD. Using this approach, we analyzed power consumption for the Ibex simple system example on the Sky130 PDK, as shown below.

Before automatic clock gating:

After automatic clock gating:

We’ve observed power savings between 8-15% for various designs. As this initial implementation uses basic heuristics, it’s possible to further extend and improve this feature in the future.

Power-efficient chip design with OpenROAD

Automatic clock gating in OpenROAD provides a quick and reliable method for reducing dynamic power dissipation. With vast experience in extending and improving OpenROAD, Antmicro can help you adopt the toolchain and customize it to reduce memory usage, decrease execution time and improve developer productivity.

If you would like to discuss how we can help you improve and automate your digital design workflows with open source tools such as Topwrap, Coverview and testplanner, reach out to us at contact@antmicro.com.