Zephyr FPGA controller

The Zephyr RTOS has seen tremendous growth recently, with almost 1000 contributors and hundreds of platforms supported. Its vendor-neutral, all-encompassing nature has let it spill into various use cases, areas and device types. One of the fields in which we have been pioneering the use of Zephyr is the context of FPGA/FPGA SoC and on the RISC-V architecture - both in hard and soft implementations. We have recently become a Platinum member of the project to underline our commitment and take a leading role in the project alongside Google, Facebook, Arm, Intel, NXP, Nordic and others.

At its core, Zephyr is a secure and lightweight real-time operating system and often an excellent choice for applications where Linux is simply too complex and where tight control over all aspects of the execution are needed. This befits especially the low-to-mid-end real time use cases in FPGA (which are often used in scenarios like ML acceleration, video transcoding etc. that require low latency), either alongside or instead of “large” OS like Linux.

Zephyr and tooling++

But Zephyr is also much more, taking an ambitious approach of providing the user with open and user-friendly tooling, (including integration with our open source simulation framework, Renode) an all-inclusive SDK, and a community that we support as long-time members of the Linux Foundation-run Zephyr Project - everything you need to get started.

The Zephyr FPGA controller which we are in the process of upstreaming into Zephyr is the latest example of Antmicro’s work to improve the developer user experience and open up new system design options.

Enabling both interactive and programmatic use, the FPGA controller allows you to work with FPGA bitstreams from Zephyr without a headache.

*** Booting Zephyr OS build v2.5.0-rc1-125-g25a1c4394db9  ***
Address of bitstream (red): 0x10000
Address of bitstream (green): 0x40000
Size of bitstream (red): 75960
Size of bitstream (green): 75960
Welcome to the bitstream switching demo! Currently blinking the LED in green. Reload the bitstream using `fpga load FPGA 75960 0x10000` to make the LED blink red.
uart:~$

Zephyr on FPGA

Originally, Zephyr primarily targeted IoT applications and FPGAs were a highly peripheral area, so small wonder there was no concept or tooling around controlling FPGAs from Zephyr applications. RISC-V, with its sudden outcrop of many excellent soft implementations of the ISA for FPGAs, together with the fact FPGAs made for an excellent development platform in the absence of silicon back in the day, changed this profoundly. As Founding members of RISC-V International we saw value in having a vendor-neutral OS choice for the vendor-neutral ISA. That is why we have been heavily involved in making the association between RISC-V and Zephyr a natural one, and many of our engagements - like the RISC-V badge developed with our partner SiFive for the 7th RISC-V workshop or work with Google’s TF Lite Micro team concerning ML acceleration - have involved running Zephyr on RISC-V in FPGA.

Zephyr FPGA controller

The FPGA controller is a completely new Zephyr subsystem developed to enable communication between Zephyr and FPGAs.

The main purpose of the FPGA controller is to enable users to control the FPGA from Zephyr and enable bitstream loading into the FPGA.

The work on the controller consisted of several parts:

• a completely new API, which enables the users to check the status of the FPGA chip, power it on or off, and change the contents of the reprogrammable logic;
• FPGA drivers, the controller currently supports the EOS S3 chip with its embedded FPGA, and Xilinx US+ FPGAs (using Antmicro’s Mercury XU port);
• a new Zephyr shell command which allows users to check the status, control and reprogram the FPGA using the Zephyr shell subsystem.

In addition to that, a new devmem load shell command has been added to Zephyr.
Users can now load arbitrary data into the onboard memory using the same transport (e.g. serial, bluetooth) that is used for the shell itself.

This ties well with the FPGA subsystem and, as described below, it can be used to easily transfer bitstream files into the memory, and later load them onto the FPGA using the new controller subsystem.

FPGA controller usage

The FPGA subsystem for Zephyr is in the process of mainlining, for now it is best to use the relevant branch of our fork of Zephyr.

Besides the Zephyr code itself, we have also prepared a usage examples repository where you can find a detailed description and guide on how to use the FPGA controller and serial loader on various hardware platforms.

This combination is especially useful for small FPGA SoCs where Linux won’t fit (like EOS S3), but can also be useful e.g. with UltraScale+ where we are using Zephyr on the Cortex-R5 cores. The UltraScale+ is at the heart of several very interesting FPGA acceleration projects we’re involved with, so stay tuned for more updates on that front.

The origin of the solution

The origin story behind the FPGA controller was as usual for Antmicro: the tool we needed for our work did not exist and so we decided to create it. As part of a collaboration with the open source-friendly FPGA vendor, QuickLogic, and Google (who are prominently supporting the open source ecosystem around FPGAs), we developed a low-cost, low-power QuickFeather board which features the EOS S3 MCU and an eFPGA SoC. More importantly, we were hired to build out the open source tooling around QuickLogic’s platform, implementing Zephyr, Renode and an open source QuickLogic FPGA toolchain, support. An open OS, simulation tools and FPGA toolchain enables co-development between the hard CPU and FPGA without the necessity of setting up complicated license servers. This approach scales perfectly in multi computer environments (including cloud server solutions).

Despite adding support for the board in Zephyr, working with the hardware, assuming you wanted to use the on-board FPGA, wasn’t very user friendly. FPGA developers had two possible approaches to reprogram the FPGA fabric:

• Uploading binaries to QuickFeather required an SWD programmer and additional tool, such as OpenOCD or SEGGER JLink, and to re-upload the bitstream the whole board had to be reset;
• Preparing a special application with a hardcoded bitstream and running it on the CPU.

Both methods require additional hardware, or non-standard software - adding unnecessary complexity.

The FPGA controller addresses exactly this problem and enables the developers to work with the FPGA hardware having nothing but the board itself and some standard, open source software installed on the computer.

Work with us

As members of both Linux Foundation and Zephyr Project, we help our customers build smart systems with modular architecture, giving developers the freedom to adjust for specific usage and easily switch to new hardware. We build a variety of open source tools, frameworks and platforms to enable cloud-to-edge AI workloads. If you need help with your FPGA or Zephyr product development, write to us to learn more at contact@antmicro.com.