7th RISC-V Workshop electronic badge by Antmicro & SiFive
The 7th RISC-V Workshop to be hosted by Western Digital in Milpitas, USA, November 28th-30th, 2017, is quickly advancing. And as always, Antmicro is preparing a few surprises especially for the occasion.
As a Founding Member of the RISC-V Foundation, Antmicro is proud to have contributed the design of a RISC-V electronic badge. Workshop speakers and members of the media will be provided with a limited edition RISC-V electronic badge developed in collaboration with SiFive and co-sponsored by the Foundation for the upcoming Workshop.
Powered by the 32-bit FE310 RISC-V CPU from SiFive, we believe this is the first electronic badge design to be completely open source from the ground up, including the SiFive FE310 RISC-V SoC that drives it.
Battery-powered and programmable over NFC from a smartphone, the RISC-V badge features an e-Ink screen to display the badgeholder’s name or whatever they will want to tell the RISC-V community.
The badge consists of a carrier card with a reusable, socket based small RISC-V SoC module that can be removed and used for prototyping other interesting RISC-V projects.
In keeping with the open philosophy underpinning the RISC-V initiative, an open, free ISA enabling a new era of processor innovation through open standard collaboration, the RISC-V electronic badge is an open source and modular design symbolic of the flexibility, extensibility and modularity of the RISC-V ISA.
All of the RISC-V electronic badge design files will be hosted on our GitHub directly preceding the Workshop.
A preliminary agenda for the 7th RISC-V workshop is now available and includes Antmicro giving a presentation on another of its RISC-V market implementations - support for a RISC-V based platform in our open source Renode virtual development framework. More on Antmicro’s presentation of Renode and Michael Gielda’s talk at the 7th RISC-V Workshop soon.
We are looking forward to welcoming you together with the RISC-V Foundation at the Workshop in a few weeks.