OpenROAD is an open source ASIC design toolchain which provides users with an autonomous workflow for various stages of chip design, from a SystemVerilog description to the final chip layout. Antmicro developed a number of improvements to OpenROAD over the past few years, namely working on features for OpenROAD’s rmp resynthesis module, which is used for design optimization. We first developed a resynthesis strategy based on simulated annealing, and, not too long ago, implemented an alternative strategy to it based on a genetic algorithm.
In OpenROAD, resynthesis relies on ABC for technology mapping (or techmapping), which is a process of converting mathematical operations into standard cells. However, ABC has a notable limitation in that regard, which is that it is only able to map single-output cells, removing the ability of working with multi-output cells such as adders.
To allow for mapping multi-output cells within resynthesis, in a recent customer project we implemented extended technology mapping from the mockturtle library to the resynthesis tool in OpenROAD. This article describes this new option for resynthesis and provides an example of how to use it.
Integrating mockturtle into OpenROAD
OpenROAD’s rmp module is used for local resynthesis, a process the purpose of which is to optimize a design. The module extracts the combinational parts of the design, exports them to ABC, which optimizes them, and the optimized logic is then inserted back into the design. We described this in more detail some time ago in an article about simulated annealing-based resynthesis in OpenROAD.
Our recent work introduces the integration of mockturtle - a library for logic synthesis and optimization - into OpenROAD. A notable feature of mockturtle, one that is crucial for the project we’re describing, is its emap command. emap, which stands for extended mapper, supports the mapping of multi-output cells during techmapping. The integration of mockturtle resulted in us adding a new command for OpenROAD, resynth_emap, which utilizes the mentioned emap.
The resynth_emap command functions just like the standard rmp module, redoing the synthesis of the combinational logic of the design with one notable change: after it extracts the logic, it then exports it into mockturtle instead of ABC. Then, it runs emap in mockturtle, which optimizes the design, and after the process is completed, the logic is reimported back into OpenROAD.
Integrating mockturtle into OpenROAD allows for performing resynthesis on designs with multi-output cells, which means that a group of single-output cells can be replaced with a single multi-output one that calculates the same function instead. To give an example, one adder cell can replace five single-output cells. This results in the need for fewer cells, and thus allows the design to be more compact. Similarly, using fewer cells overall means fewer wires, which reduces the total chip area even further. A smaller amount of wires contributes to making the process of routing them easier, and it may even result in a potential improvement of timing. Using a multi-output cell can also contribute to reduced power consumption, as a single, bigger cell can potentially draw less power than a collection of multiple cells performing the same task. The specific gains, naturally, depend on the design itself as well as the design process; nevertheless, implementing multi-output cells can have meaningful benefits for chip designs.
Mapping multi-output cells in OpenROAD with mockturtle
The example below performs resynthesis on the jpeg_encoder design targeting the open source SKY130 PDK.
First, we’ll run openroad as an interactive shell. Load the design:
define_corners fast slow
read_liberty -corner slow sky130/sky130_fd_sc_hd__ss_n40C_1v40.lib
read_liberty -corner fast sky130/sky130_fd_sc_hd__ff_n40C_1v95.lib
read_lef sky130/sky130hd.tlef
read_lef sky130/sky130hd_std_cell.lef
read_verilog jpeg_sky130hd.v
link_design jpeg_encoder
read_sdc jpeg_sky130hd.sdc
source sky130/sky130hd.rc
set_wire_rc -signal -layer met1
set_wire_rc -clock -layer met3We’ll look at its statistics.
report_cell_usage
report_wns
report_tnsAs seen below, the design has 45 633 cells and 447 070 µm² of area:
Cell type report: Count Area
Buffer 1561 5880.64
Inverter 9945 37329.55
Sequential cell 4380 88011.91
Multi-Input combinational cell 29747 315847.92
Total 45633 447070.03
wns max 0.00
tns max 0.00Now, run resynth_emap with multi-output cell mapping enabled:
resynth_emap -scene fast -map_multioutput
report_cell_usage
report_wns
report_tnsAfter it finishes, we get these results:
Extended technology mapping stats:
area: 314862.562
multioutput gates: 6902
Cell type report: Count Area
Buffer 2 11.26
Inverter 4095 15370.99
Sequential cell 4380 88011.91
Multi-Input combinational cell 35750 299586.81
Total 44152 402968.98
wns max -113.61
tns max -293313.006 902 multi-output cells were mapped, and area dropped from 447 070 to 402 969 µm² - a 10% reduction.
Timing no longer closes, so we’ll run repair_timing to fix the violations by upsizing drivers and inserting buffers:
repair_timing
report_cell_usage
report_wns
report_tnsAfter repair, timing is closed, and the area gain is preserved:
Cell type report: Count Area
Buffer 2 11.26
Inverter 4095 15370.99
Sequential cell 4380 88011.91
Multi-Input combinational cell 35677 299614.59
Total 44154 402997.76
wns max 0.00
tns max 0.00Optimize your chip designs with OpenROAD
With the implementation of mockturtle’s extended techmapping, Antmicro continues to help improve the process of resynthesis in OpenROAD, allowing for the creation of better optimized chip designs. We also help customers integrate OpenROAD into their workflow and adapt it to their specific needs.
If you wish to learn about Antmicro’s services surrounding tools for ASIC design or would like to know more about how we can help you with your design process, reach out to us at contact@antmicro.com.
