Renode’s advanced co-simulation capabilities enable efficient, deterministic testing of hardware/software before the actual silicon is available. These capabilities make it especially effective for validating physical systems in virtualized environments across a variety of use cases - from simulating heterogeneous multi-core ASICs to testing complex, multi-node systems that are commonly used in modern safety-critical applications.
Renode enables simulation on different levels of abstraction: you can use its collection of plug-and-play building blocks to run a fast, functional simulation of your hardware systems, or perform a cycle-accurate simulation of HDL designs thanks to its integration with RTL simulators like Verilator. In the context of functional simulation, the SystemC support we introduced some time ago enables direct integration of Renode into SystemC-based workflows, significantly expanding the range of use cases and tools it can support.
Recently, our collaboration with Analog Devices on improving their SystemC Virtual Platform strategy has brought a range of new features to Renode’s SystemC integration. We have introduced support for the DMI and debug transport interfaces, enabled generic payload extension (now used in the context of Arm Cortex-M TrustZone), and also extended Renode’s capabilities in leveraging native connection with SystemC. Additionally, the SystemC bridge can now handle multiple CPU cores, which simplifies integration of multiple Renode-driven CPUs in a single SystemC simulation.
This blog note covers the latest improvements to SystemC co-simulation in Renode, which allow performing comprehensive testing of your SystemC-based models and enable seamless integration of Renode with other simulators as part of your custom workflows.
Introducing support for the Direct Memory Interface
The major improvement that we made to SystemC integration in Renode is Direct Memory Interface (DMI) support, which can significantly accelerate memory transactions for high throughput simulations. DMI allows bypassing the transport interface for read and write transactions: values in memory are instead accessed and updated via pointers, eliminating the need to go through expensive b_transport or nb_transport function calls.
You can check an example of the introduced DMI native interface and explore our implementation of this feature in the Renode repository.
Enabling the Debug Transport Interface
One of Renode’s strengths is its transparent, fully-controlled debugging process that builds on Renode’s extensive tracing features and supports easy integration into IDEs, such as VS Code.
We have further enhanced Renode’s debugging functionality in the context of SystemC integration by introducing support for the Debug Transport Interface (DTI). Its transport_dbg method allows performing memory accesses on behalf of a CPU without triggering side-effects inherent to the b_transport method. This mechanism is exposed by the sysbus API in the built-in scripting engine and is also used internally by the semihosting handler. By using Renode’s GDB support, you can now examine memory inside the simulation without affecting its state.
You can check our implementation of the DTI support in the Renode repository.
Generic payload extension for the Arm TrustZone context
Besides the basic transaction information such as read/write access and width (1/2/4/8 bytes), the SystemC TLM-2.0 standard allows passing extra information in payloads for use by interested implementers. This is an optional feature that does not break interoperability with any generic simulators.
We have taken advantage of this capability and extended the scope of the generic payload in Renode so that it now passes the security state of Cortex-M cores with support for the Arm TrustZone technology.
In Renode, we support making access to peripherals conditional on such aspects of the CPU state as:
busSecure: means that the access is considered Secure by the Secure Attribution Unit (SAU) or the Implementation Defined Attribution Unit (IDAU).privileged: reflects the current execution state of the CPU.semihosting: a new parameter that we recently added. It’s set when the semihosting debugger makes a memory access on behalf of the CPU.
This change improves the fidelity of your simulation process - for instance, the SystemC interconnect can use payload data to fail transactions which have incorrect permissions, just like on your real hardware.
You can check our implementation of the generic payload extension for the TrustZone context for more detail.
Multi-core support in the SystemC bridge and a native connection with SystemC
We have also enabled multi-core support in the SystemC bridge. The CPU context is particularly important for interconnects as it allows differentiating accesses by various initiators - this is specifically valuable, for instance, when there’s a need to selectively grant access to a chosen peripheral.
Now, the ID of a CPU initiator is handled by the provided SystemC library, where we treat unique CPU initiators as separate SystemC modules. As a result, you can use multiple CPU cores modeled in Renode and easily integrate them in a single SystemC simulation.
CPU signals (interrupt requests, core_reset_in, cpu_wait, O_sleeping, O_lockup, and more) are now available for use from SystemC, and it’s also possible to control the CPU’s clock frequency using a SystemC signal.
Furthermore, we have recently made multiple improvements to the accuracy of ARM Cortex-M emulation, including support for the architectural Lockup state and many associated improvements to exception handling. Fault escalation and tail-chaining are faithfully modeled.
Finally, you can now host Renode in the same process as the SystemC Simulation Kernel by leveraging the in-process native transport without TCP socket overhead. The ability to build Renode as a native library makes it possible to manage the whole Renode lifecycle, from launch to shutdown, within the same process using a C/C++ API. An example of hosting Renode in a sample C program is available in our GitHub repository.
Accelerate your digital design workflow with Renode
The improvements to SystemC integration in Renode, which were introduced as part of our recent commercial project, enable faster simulation and more efficient execution of SystemC-based models. With these changes in place, Renode becomes more accessible to silicon developers who rely on long-established or highly customized simulation environments as they can now easily integrate it into their development and simulation workflows.
As part of our commercial services, we offer engineering assistance and technical guidance across the whole digital design flow, helping you accelerate pre-silicon architectural exploration and development, co-simulate software and hardware for faster product turnaround, perform deterministic testing of your simulated systems, and easily integrate Renode with external IDEs and tools of your choice.
If you would like to bring Renode into your workflows and extend to new use cases, or use our technical expertise to accelerate your ASIC development process, reach out to us at contact@antmicro.com.
