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Open hardware DC‑SCM designs
Covering DC‑SCM rev. 1.0 and rev. 2.1, with SoC and FPGA from multiple silicon vendors.
Open hardware DC‑SCM 2.1 OpenBMC FPGA LTPI DC-MHS
Scalable, secure and customizable DC‑SCM solutions for server management
Antmicro helps design, verify and implement server management hardware and software compatible with the OCP DC‑SCM specification: from flexible dedicated SoC and FPGA-based designs and open source reference platforms, through OpenBMC integration and debugging tools, to complete server setups.
DC‑SCM 2.1 reference platform
Agilex 5 Modular DC‑SCM
New
OpenBMC on OCP servers
DC-SCM at a glance
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Bring-up and debugging tools
Breakout board, DC-SCI interposer, eSPI adapter and eSPI decoder for lab-side development before deployment.
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Years of DC‑SCM experience
Numerous open and proprietary DC‑SCM designs, many OCP demos, reference platforms and servers integrated.
Hardware architecture
We make custom-designed DC‑SCM solutions for flexible and configurable server management
Many of our DC‑SCM designs are released as open hardware: proven, well-described starting points for PoCs and custom designs tailored to and integrated with your server platform.
DC‑SCM rev. 2.1 New
Agilex 5 Modular DC‑SCM Carrier Board
A Carrier Board built together with Altera for the Agilex 5 E-Series FPGA and SoC family: a replaceable MitySOM-A5E Mini module lets you pick any pin-compatible 5E variant and scale performance as your needs grow.
New · Built with Altera
Agilex 5 Modular DC‑SCM Carrier Board: open hardware server management that scales with your needs
Together with Altera, we created a new open hardware DC‑SCM Carrier Card for Agilex 5 E-Series SoC FPGAs. The Linux-capable Hard Processor System runs OpenBMC, while the FPGA fabric provides a hardware abstraction layer and signal processing close to the DC-SCI interface. Swap the module to move between pin-compatible 5E variants and streamline your DC‑SCM development.
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Arm Cortex-A76 + A55 HPS
Dual-core Cortex-A76 up to 1.8 GHz and dual-core Cortex-A55 up to 1.5 GHz, with up to 656k Logic Elements.
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Modular and scalable
Replaceable 28 × 50.8 mm MitySOM-A5E Mini module with up to 8 GB LPDDR4 and 32 MB QSPI flash.
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Standards-compliant
DC‑SCM 2.1 interface and outline, designed to the OCP HPM Common Circuit Type 1 Design Specification.
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OpenBMC-ready
Yocto-based OpenBMC with sensors, D-Bus services and the WebUI configured for the hardware platform.
Developing OpenBMC for a real DC‑SCM board, without a physical HPM: sensor example
The Agilex 5 Modular DC‑SCM Carrier Board paired with our DC‑SCM Breakout Board lets you develop and validate OpenBMC features on the bench, mocking the relevant parts of the target HPM.
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Mock the HPM
A TMP75 temperature sensor on the DC‑SCM Breakout Board is connected to an I2C bus exposed on the DC-SCI connector.
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Route through the FPGA
The programmable logic routes the I2C bus from the DC-SCI pins to the Hard Processor System running OpenBMC.
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Describe in Yocto
A devicetree node, a phosphor-hwmon configuration and an inventory association publish the sensor on D-Bus.
dc-scm-breakout-board.confLABEL_temp1 = "DC_SCM_Breakout_Board" WARNHI_temp1 = "25000" CRITHI_temp1 = "40000" - 04
Monitor in the WebUI
The sensor is picked up automatically by the OpenBMC WebUI, with warning and critical thresholds.
Sensors
Sample dataNominalDC-SCM Breakout Board
32.375°C
Temperature history
°C · Last 30 minutesTemperature
System integration
Providing help with software development, hardware abstraction and system integration
We work across the whole server stack, from hardware, through FPGA IP and integration and low-level board support to OpenBMC and security features and complete, booted and production-ready server platforms.
We develop FPGA IP such as LVDS Tunneling Protocol and Interface between FPGAs on the DC‑SCM and the HPM, passing I2C, GPIO, UART and other low-speed signals over four differential pairs. Routing all control signals through the FPGA pair introduces a hardware abstraction layer: different server configurations can be supported just by switching FPGA payloads.
Read about LTPI supportDC-MHS PnP FRU definitions describe the internal structure of a server. They can be used in a discovery stage where the DC‑SCM FPGA reads the FRU JSON from the EEPROM on the HPM and reconfigures itself to match the LTPI signal mapping before the host starts booting.
Read about FRU supportWe build and customize Yocto-based OpenBMC distributions for SoC and FPGA-based BMCs: board support, devicetrees, phosphor-hwmon sensors, inventory and D-Bus services, fan control and the WebUI, integrated with our OTA and testing frameworks.
Read about the reference platformA 90 × 70 mm board compatible with DC‑SCM 2.x modules that exposes LTPI, PCIe, USB, UART, SPI, QSPI and I2C to aid software development, debugging and pre-deployment validation. It powers the DC‑SCM on the bench and can be adapted to mimic a target HPM or rack management system.
View on Open Hardware PortalDC-SCM
FPGA CertusPro-NX
I2CGPIOUARTSGPIO
LTPI tunnel
Data →
Clock →
← Data
← Clock
HPM
FPGA MachXO3D
I2CGPIOUARTSGPIO
Server debugging tools
We develop tools that support server debugging in a controlled environment, helping verify functionality before deployment
eSPI analyzer Logic 2 · decoded frames
GET_STATUS ACCEPTPUT_VWIRE ACCEPT
CS#CLKIO0IO1ALERT#
eSPI decoder plugin for Logic 2
An open source plugin for Saleae's Logic 2 signal analyzer software, decoding eSPI transactions for debugging and inspection of CPU-BMC communication.
DC-SCI Debug Interposer
A passthrough board placed between the DC‑SCM and the HPM that exposes all single-ended DC-SCI signals on pin headers, with SOP-16 sockets for easy BIOS injection.
Use case
Booting servers using our open source toolkit and hardware
Using open source DC‑SCM hardware, OpenBMC and our debugging tools, we develop complete demonstration and reference platforms with OCP-compliant servers.
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Reference platform
Hardware platforms like the DC‑SCM OSM-L Carrier Card with the OSM-L BMC SoM can be used to control the low-speed signals and run OpenBMC.
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Access to DC-SCI
The DC-SCI Debug Interposer provides easy access to DC-SCI signals, letting us inject eSPI and LTPI signals and serve the BIOS to the server.
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eSPI troubleshooting
Our eSPI Debug Adapter and the eSPI decoder plugin provide a way to troubleshoot problems with eSPI signals.
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Thermal management over LTPI
OpenBMC on the DC‑SCM can read temperature sensors and control e.g. chassis fans through I2C buses tunneled via LTPI.
System Designer
Describe, visualize and document complete server systems
System Designer combines a library of hardware components and reference designs with multi-node diagrams of servers, power distribution, cooling and rack management. Our open source Fru2Graph tool turns DC-MHS PnP FRU JSON files into interactive graphs of every interface and connection within the system.
Custom engineering
We help you build secure, flexible server management infrastructure, end to end
Custom DC‑SCM and server hardware
Our open hardware platforms are fully customizable in terms of interfaces, component layout and PCB outline, and we design anything from single baseboards to complete clusters.
FPGA IP and hardware abstraction
LTPI implementations, signal routing and reconfigurable FPGA payloads that let one DC‑SCM support many HPMs.
OpenBMC and BSP integration
Yocto-based OpenBMC and Zephyr ports, sensor and inventory configuration, OTA updates with RDFM.
Security and Root of Trust
RTL, DV and software development for open source Root of Trust projects including Caliptra and OpenTitan for e.g. BMC chips.
Testing and validation
Simulation with Renode, automated hardware testing with Protoplaster and memory security testing with Rowhammer tester.
System description
DC-MHS FRU-based descriptions in System Designer as a single source of truth shared by hardware, software and mechanical teams.
Blog
Our latest developments around DC‑SCM and open server management
Build a DC‑SCM platform tailored to your server architecture and management requirements
Get in touch to discuss custom DC‑SCM hardware, software and FPGA IP development.