RISC-V

We use RISC-V to build advanced computer systems and help our customers reap the benefits of this disruptive technology.

LEVERAGE RISC-V AND THE OPEN SOURCE ECOSYSTEM

As a Strategic Founding member of RISC‑V International and an early adopter of the ISA, we are well versed in using RISC‑V its ecosystem, which we heavily contribute to as well.

BUILD A RISC-V SYSTEM

Tap into Antmicro’s RISC­V expertise to build a modern system that optimizes processes in verticals such as industrial inspection, medical, automotive, drones and more.

Software

Tooling

ASIC & FPGA

ANTMICRO’S RISC-V PROJECTS

Machine Learning on RISC-V in Renode with TensorFlow Lite

In collaboration with Google, we’ve enabled their machine learning framework TensorFlow Lite to be run on a soft RISC-V MCU and in our open source simulator Renode, broadening its application field and allowing the TF Lite team to develop ML applications in Continuous Integration test-driven environment.

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Zephyr / RISC-V softcore implementations

We use the robust, lightweight and secure Zephyr RTOS in many customer projects. As a Zephyr Project member, we are authors of numerous additions to Zephyr for the RISC-V architecture.

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RISC-V based 32-bit Core-V MCU

We have been collaborating with QuickLogic and the Core-V ecosystem to develop an FPGA SoC with open source FPGA tooling and Renode support.

Microchip PolarFire

Microchip’s PolarFire FPGA SoC is the world’s first mass-market Linux-capable RISC-V implementation. In a partnership with Microchip we added full pre- and post-hardware support for their platform in Renode and enabled a test-driven software development methodology for their RISC-V based CPUs.

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CI-driven flows for ASIC and FPGA development

As a Platinum Member of CHIPS Alliance, together with our customers such as Google, Western Digital and QuickLogic we are developing open source tools enabling CI-driven flows in hardware development.

Open source synthesis of RISC-V CPUs

We’ve enabled using SystemVerilog on RISC-V cores and SoCs and in other practical use cases, such as lowRISC’s ibex, 32-bit RISC-V core used in Google’s open source security project OpenTitan.

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SkyWater PDK

In a historic development that involved SkyWater Technologies, Google and Antmicro, the first ever process design kit (PDK) was released as open source, adding fuel to the quest towards truly open source chips started by the RISC-V community.

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RISC-V based SoC design / advanced FPGA systems

We often work with LiteX, an open source library for building complex SoCs. It supports a number of RISC-V cores, e.g. VexRiscv featuring multi-core capability developed by Antmicro.

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System-in-package design

GEM chiplet technology featuring RISC-V MCU’s, showcasing Antmicro’s capability to rapidly build ASICs for specific tasks.

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Triple Modular Redundancy demonstrator

An open source, RISC-V-based Triple Modular redundancy concept built for Thales.

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Renode is our open source simulator for designing complex devices. With extensive RISC-V support and the ability to simulate all hardware levels, Renode streamlines the engineering process of RISC-V based or heterogeneous systems.

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