OPEN ASICS, OPEN FPGA, OPEN SOURCE TOOLS
OPEN ASICS, OPEN FPGA, OPEN SOURCE TOOLS

AUTOMATING DIGITAL DESIGN AND VERIFICATION TRACKING WITH TESTPLANNER

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Testplanner illustration

In digital design, ensuring systematic verification of all design aspects requires not only proper planning of design verification and test development, but also tools to track and make sure that design development and verification goes according to the...

OPEN HARDWARE
OPEN HARDWARE

SCALABLE AND EXPANDABLE AUDIO LATENCY TESTING PLATFORM FOR AR/XR DEVELOPMENT

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Audio Latency Tester

Audio and video latency is a key factor in determining the quality of the user experience in communication services. With eXtended Reality (XR) systems gaining popularity in entertainment as well as professional applications such as training, education...

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

IMPROVING VERILATOR'S HIERARCHICAL MODE FOR BETTER PERFORMANCE AND SCALABILITY

Published:

Hierarchical verilation improvements

Antmicro has been providing engineering support for Verilator in a variety of ASIC-related projects, which often include complex, state-of-the-art designs and take a lot of time time and memory to run. Normally, when generating C++ code (a.k.a. verilating...

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