Press release: Antmicro reveals partnership with Thales on the disruptive RISC-V open ISA
Topics: Open FPGA IP, Open ISA, Open OS
Companies announce partnership and present first demonstrator of a fault-tolerant RISC-V space application at the RISC-V Workshop in Barcelona
Barcelona - May 8th, 2018 - Today at the RISC-V Workshop in Barcelona, Antmicro, a software-driven high tech company developing leading industrial cyber-physical and edge AI systems, and a Platinum Founding Member of the RISC-V Foundation, has publically announced its partnership with Thales around the disruptive RISC-V open processor architecture. The companies have joined efforts to drive RISC-V into global academia and the industry at large by introducing the RISC-V paradigm into the aerospace prime’s technology tree.
“We are thrilled to be among the first technology leaders working with Thales on bringing RISC-V to the wider Thales family”, said Michael Gielda, VP Business Development at Antmicro. “The fact that Thales is working with us to release the TMR RISC-V demonstrator and the related training materials on an open source license is an encouragement for the global industry to embrace the multifaceted technological advance that comes with the world switching to open standards on a level as fundamental as silicon.”
“RISC-V adoption continues to be driven by the needs of end applications and the Antmicro / Thales collaboration is a great example of industry, technology and academia coming together to facilitate the much awaited change in computer architecture and design”, Rick O’Connor, Executive Director of the non-profit RISC-V Foundation, explains.
“Thales is looking forward to exploring possible applications of RISC-V in the space and other domains together with Antmicro. We view them as an important asset in the RISC-V ecosystem, joining the world of chip, FPGA and software development with a software-driven vision firmly grounded in open source”, Bertrand Tavernier, VP Software Technologies at Thales, adds.
The Triple-Modular-Redundancy RISC-V demonstrator has been designed to show how the open RISC-V ISA architecture specification, and an open source implementation thereof, can be used to build a flexible and extendible fault-tolerant voter CPU system mitigating Single Event Upset (SEU) with minimum impact on software.
A wide array of technologies is employed in the demonstrator project to achieve Triple-Modular-Redundancy in relatively short time, and to serve as a future-proof development and training platform. RISC-V lies at the base of the solution, enabling the customized CPU demonstrator to be managed with off-the-shelf, open source tools developed by the entire RISC-V ecosystem.
The Rocket Chip Generator, coming out of University of California, Berkeley, is used to develop the RISC-V cores that are part of the solution without having to build them from scratch but rather focusing on the relevant functionality. The Scala-based Chisel HDL, also a Berkeley development, is used for high-productivity IP development and easy-to-explain code. Zephyr - whose port for RISC-V is maintained by Antmicro - is used on the redundant cores as a standard RTOS, to provide a software stack that is significantly more complicated than a bare-metal program but also realistic in a potential real-life application. Linux on Antmicro’s UltraScale+ Processing Module is used to build a very robust and future-proof development platform with lots of FPGA logic, I/O and tooling available.
The demonstrator is currently being presented at the RISC-V Workshop at the Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, following Antmicro’s announcement of 64-bit support of RISC-V targets in Renode, their open source software development framework for multinode systems, to enable a wider adoption among RISC-V developers worldwide.
Antmicro has been assisting partners globally with RISC-V early adoption projects through developing Proofs of Concept, prototyping, hardware design, porting OS, drivers, buildsystems, custom FPGA peripherals and integration.
The company’s partnership with Thales is another step in Antmicro’s strategy and commitment to becoming a leading technology provider of RISC-V solutions.
Antmicro is a software-driven tech company developing leading edge cyber-physical and edge AI systems for various branches of industry. With cross-competence in software, full-stack FPGA SoC development and high-end hardware, Antmicro provides applied R&D for customers worldwide, offering assistance in prototyping, new product development and adoption of modern embedded technologies in applications from robotics, drones, aerospace, defence and civil security to portable industrial, broadcasting and medical devices. The vast majority of Antmicro’s projects include a broad range of open source technologies such as RISC-V, Renode, Zephyr, Linux, Android, ROS, TensorFlow and Caffe. Antmicro is a Platinum Founding Member of the RISC-V Foundation, introducing an open Instruction Set Architecture for a new era of processor innovation through open standard collaboration. Visit www.antmicro.com.
With 65,000 employees in 56 countries, Thales reported sales of €15.8 billion in 2017.
Within Thales’s global R&D organisation, some 3,000 people are dedicated to fundamental research and technology (R&T) projects. Thales’s R&T teams are mainly based in France, United Kingdom, Netherlands, Canada, Australia, and Singapore.
In France, the Palaiseau research laboratory, located on the campus of the École Polytechnique, is part of the world-class science and technology Paris-Saclay cluster.