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OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN SIMULATION

HIGH-FREQUENCY HARDWARE DESIGN WITH OPEN SOURCE SIGNAL INTEGRITY ANALYSIS

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VSD block diagram of the data processing flow Hardware design of advanced video processing devices is one of the key areas of activity at Antmicro. With a never-ending pursuit of higher data throughput, signal integrity moves to the forefront of challenges in modern PCB...
OPEN SOURCE TOOLS, OPEN OS, OPEN ISA

RENODE 1.14 WITH ARMV8 SUPPORT, IMPROVED CO-SIMULATION AND NEW PLATFORMS

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Renode 1.14 illustration Antmicro is happy to announce the next, 1.14 release of our open source Renode simulation framework, including lots of new developments originating from both customer and R&D projects, along with community contributions. Since...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

DPI SUPPORT IN RENODE FOR HDL CO-SIMULATION WITH VERILATOR AND QUESTA

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DPI support in Renode for HDL co-simulation Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable gate arrays (FPGAs) and application-specific integrated circuits...
OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN FPGA, OPEN ASICS

BUILD EMBEDDED SYSTEMS INTERACTIVELY WITH ANTMICRO'S VISUAL SYSTEM DESIGNER

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Visual System Designer Customers interested in building new industrial or consumer devices, typically involving one or more PCBs and based on Linux, Zephyr or Android (or even all of them at the same time), often approach Antmicro before they know...
OPEN SOURCE TOOLS, OPEN MACHINE VISION

GITHUB ACTION FOR V4L2 APPLICATION TESTING IN RENODE

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GitHub action for v4l2 application testing illustration Antmicro’s work with camera systems often results in new reusable tools and libraries helpful for debugging video devices and applications. Some examples of such tools for working with v4l2 pipelines such as grabthecam, farshow
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

CPU RTL CO-SIMULATION IN RENODE

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CPU RTL co-simulation in Renode Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to cover ASIC and FPGA SoC development...
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