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chips-alliance

OPEN FPGA, OPEN ASICS

DYNAMIC SCHEDULING IN VERILATOR - MILESTONE TOWARDS OPEN SOURCE UVM

Published:

Dynamic scheduling in Verilator UVM is a verification methodology traditionally used in chip design which has historically been missing from the open source landscape of verification-focused tooling. While new, open source approaches to verification have...
OPEN ISA, OPEN ASICS

ANTMICRO’S ARVSOM RISC-V MODULE ANNOUNCED

Published:

ARVSOM We are excited to announce the ARVSOM - Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71x0 SoC. Using the RISC-V architecture, which Antmicro has been heavily involved in since the early...
OPEN FPGA, OPEN SOURCE TOOLS, OPEN ISA

OPEN SOURCE FPGA TOOLS AND RENODE SUPPORT FOR CORE-V MCU

Published:

Core-V and Renode For over a year now we have been working together with QuickLogic towards supporting their FPGA devices in open source FPGA tooling. This is the first time in history where an FPGA vendor has gotten directly involved in enabling...
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