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chips-alliance

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

POWER ESTIMATION IN OPENROAD USING THE SAIF WAVE FORMAT IN VERILATOR

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Power estimation with Verilator and OpenROAD Power consumption is a major aspect of chip design, and the ability to reliably and efficiently predict it can save a lot of engineering cycles. While it is difficult to predict the exact consumption upfront without delving...
OPEN ASICS, OPEN FPGA, OPEN SOURCE TOOLS

AUTOMATING DIGITAL DESIGN AND VERIFICATION TRACKING WITH TESTPLANNER

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Testplanner illustration In digital design, ensuring systematic verification of all design aspects requires not only proper planning of design verification and test development, but also tools to track and make sure that design development and verification...
OPEN SOURCE TOOLS

AUTOMATED AND STANDARDIZED SOFTWARE BENCHMARKING WITH BENCHALOT

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Benchalot illustration The growing complexity of the hardware Antmicro helps its customers build and deploy software workloads on requires continuous benchmarking and optimization to track, understand and fix performance bottlenecks. In our work...
OPEN SOFTWARE LIBRARIES, OPEN SOURCE TOOLS

10 HRS TO 37 MINS - OPTIMIZING LLVM FOR MACHINE-GENERATED C++ CODE

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Verilator and LLVM logos with a speedometer in the middle While helping customers automate and optimize their workflows, especially in complex use cases like ASIC design, Antmicro often finds itself building and enhancing multi-layered code generation infrastructure, HLS tools, transpilers...
OPEN HARDWARE, OPEN ASICS

INTRODUCING ANTMICRO’S OPEN SOURCE MYRA SYSTEM-IN-PACKAGE

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Photo of the Myra SiP and baseboard System-in-Packages (SiP) are a way of enclosing multiple integrated circuits into a single component package, often used in space-constrained consumer applications like in wearables or cell phones or miniaturized, environment...
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