OPEN SOURCE TOOLS, OPEN FPGA, OPEN ISA
ADVANCED CO-SIMULATION WITH RENODE AND VERILATOR: POLARFIRE SOC AND FASTVDMA
Published:
Co-simulating HDL has been possible in Renode since the 1.7.1 release, but the functionality - critical for hardware/software co-development as well as FPGA use cases - is constantly evolving based on the needs of our customers...
