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verilator

OPEN SOURCE TOOLS, OPEN FPGA

ADVANCED CO-SIMULATION WITH RENODE AND VERILATOR: ZYNQ AND FASTVDMA

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Diagram depicting co-simulation of Zynq Co-simulation is extremely useful for developing complex systems, especially those targeting FPGA SoCs, where specialized IP cores often interact with advanced software running on the hard CPU. Co-simulation has been available...
OPEN FPGA, OPEN ISA, OPEN HARDWARE, OPEN SOURCE TOOLS

CHIPS SWERV CORES AND THE OPEN TOOLS ECOSYSTEM

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Antmicro and CHIPS Alliance logos Antmicro’s open source work spans all parts of the computing stack, from software and AI, to PCBs, FPGAs and, most recently, custom silicon. We connect those areas with an overarching vision of open source tooling and methodology...
OPEN FPGA, OPEN SOURCE TOOLS, OPEN ASICS

AN OPEN SOURCE SYSTEMVERILOG TEST SUITE

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SystemVerilog logo At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools. Verilog, SystemVerilog and open tooling
OPEN SOURCE TOOLS, OPEN FPGA

CO-SIMULATING HDL MODELS IN RENODE WITH VERILATOR

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Renode - Verilator UARTLite co-simulation demo Antmicro’s open source simulation framework, Renode, was built to enable simulating real-life scenarios - which have a tendency to be complex and require hybrid approaches. That’s why, besides other things, the Renode 1.7...
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