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risc-v

OPEN TOOLCHAIN, OPEN OS, OPEN AI, OPEN FPGA IP

TENSORFLOW LITE IN ZEPHYR ON LITEX/VEXRISCV

Published:

TensorFlow Lite and Zephyr logos While much of the focus for the recent developments in AI has been on cloud-centric implementations, there are many use cases where AI algorithms have to be run on small and resource constrained devices. Google’s TensorFlow...
OPEN FPGA IP, OPEN TOOLCHAIN, OPEN ASICS

AN OPEN SOURCE SYSTEMVERILOG TEST SUITE

Published:

SystemVerilog logo At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools. Verilog, SystemVerilog and open tooling
OPEN TOOLS, OPEN NETWORKING, OPEN FPGA IP

RENODE 1.8 RELEASE WITH MULTI-CORE GDB SUPPORT AND NEW RISC-V PLATFORMS

Published:

Renode 1.8 The newest release of Renode, Antmicro’s open source multi-node simulation framework, adds new exciting pieces to your toolbox, along with support for even more RISC-V platforms and CPUs. With these new capabilities it’s even...
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