Published:
We are happy to announce our involvement in ‘Very Efficient Deep Learning in IoT’ (VEDLIoT) - a project funded by the European Commission and coordinated by Bielefeld University’s CoR-Lab, launched at the end of 2020. Comprising...
Published:
Throughout 2020 we have been hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe...
Published:
For over a year now we have been working together with QuickLogic towards supporting their FPGA devices in open source FPGA tooling. This is the first time in history where an FPGA vendor has gotten directly involved in enabling...
Published:
As more and more companies, organizations and educational institutions are using Renode’s hardware simulation and testing capabilities, we get a lot of questions along the lines of “Can I run my board in Renode and how complicated...
Published:
The virtual RISC-V Summit is approaching fast, promising to put a spotlight on a range of interesting, real-life use cases and implementations of the groundbreaking open source processor architecture, with a number of informative...
Published:
It is becoming evident that the next level of advancement in chip-building can be achieved through open, modular and collaborative methodologies resulting in unmatched flexibility, ease of development and robustness of the...
