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risc-v

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

CPU RTL CO-SIMULATION IN RENODE

Published:

CPU RTL co-simulation in Renode Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to cover ASIC and FPGA SoC development...
OPEN OS

SEL4 USERSPACE DEBUGGING WITH GDB EXTENSIONS IN RENODE

Published:

Diagram depicting CAmkES sample application architecture Debugging is an integral part of the embedded systems development process especially in the context of userspace applications running inside an OS, where it can be difficult to follow the flow of the code. OS-aware debugging...
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