Antmicro sponsors ORConf 2019 with talks on Renode and open FPGA tooling
Being part of the ORConf community since its early days, we’re happy to once again sponsor the event, this time hosted on September 27th-29th, 2019 in Bordeaux, France (https://orconf.org/).
With Antmicro’s CEO Peter Gielda having joined the FOSSi Board of Directors earlier this year, we confirm our dedication to open source, and will help to advocate the recent developments on all its exciting fronts.
Following what has been an exciting year for open standards, we’ll be touching on topics such as the vision behind Antmicro’s gold membership in CHIPS Alliance, further adoption of RISC-V by our partners and customers and a variety of open source tools and demonstrators we’ve been consequently releasing to GitHub.
The full schedule has just been announced, but a quick overview of Antmicro’s talks at ORConf 2019 should be enough to spark your attention.
Renode - open source simulation for rapid development of complex systems, coming to a cloud near you
Join us on Saturday, September 28th at 11:30 AM for Michael Gielda’s talk entitled “Renode - open source simulation for rapid development of complex systems, coming to a cloud near you”, explaining the new, cloud-powered capabilities our open source simulation framework Renode.
Renode has been available as a permissively licensed desktop simulation framework for (unmodified) software development and HW/SW co-development in complex systems - including multi-node, heterogeneous multi-core and multi-architecture ones - for some years now.
Besides a host of awesome recent developments in version 1.8 such as physical FPGA and Verilator co-simulation, enhanced multi-core debug, support for many new RISC-V platforms, Renode has also some big changes to announce.
The collaborative nature of virtual development - with features such as state saving, event storing/replaying, synchronous debug of multi-node environments and simply being able to share your work with colleagues using a bunch of files - is best experienced in a cloud environment, where resources can be truly shared and easily scaled. In this talk, we’re announcing the Renode Cloud Environment, an open source design, testing and CI system that builds on and integrates with Renode.
Generating Versatile Place and Route (VPR) device models generation from Verilog with V2X
Later on Saturday at 2:00 PM we’ll have Karol Gugala, Engineering Manager at Antmicro, present on open tooling with “Generating Versatile Place and Route (VPR) device models from Verilog with V2X”.
The presentation will discuss the problem of creating FPGA device architecture definitions for the Versatile Place and Route (VPR) tool. VPR describes the architecture using XML files, which can become quite complicated and require additional work to create.
V2X addresses this by allowing to generate the architecture description from Verilog files. The Verilog device models are often created separately to architecture definition as simulation models, or technology mappings. With V2X, architecture definition can be created directly from those files, reducing the work involved in adding support for a new FPGA architecture.
V2X is currently used in the Symbilflow project, but the tool itself is designed to enable generating architecture descriptions of any FPGA vendor.
Antmicro’s recent open source initiatives
Antmicro’s work is deeply rooted in open source, as confirmed by our leadership in major open source initiatives, from Linux Foundation, RISC-V Foundation, FOSSi Foundation, The Zephyr Project, to the more recent CHIPS Alliance. To keep up to date with our open source activity, make sure you follow our GitHub and Tech Showcase. Check out our recent contributions such as Fast Versatile DMA: an open, portable & vendor-neutral DMA controller and Co-simulating Verilog IP with Renode & Verilator, which features a demo of a RISC-V peripheral running Zephyr.
If you’d like to schedule a meeting at ORConf, write to firstname.lastname@example.org.