Antmicro exhibits at RISC-V Summit 2019: Renode, Fomu and open chip design
Topics: Open ISA, Open OS, Open networking
RISC-V Foundation Platinum Founding Member Antmicro will be exhibiting at RISC-V Summit 2019, the annual global conference for the disruptive open ISA that is paving the way for open digital design. The show will be hosted in the San Jose Convention Center, California, from December 10th to 12th, and as always, Antmicro is announcing a significant presence there.
Renode: the open source RISC-V (and more!) simulation framework, coming to a cloud near you
Joining our customers and partners (CHIPS Alliance, Microchip, Western Digital, SiFive, zGlue and others) on the exhibition floor, visit Antmicro at our dedicated booth #202 for exciting live demos, including the recently announced Renode Cloud Environment.
At last year’s RISC-V Summit we released a complete Renode-based simulation platform for Microchip’s PolarFire SoC with five 64-bit RISC-V cores and interfaces like PCI Express, Ethernet, CAN, USB etc. This platform joined a host of other supported SoCs and boards from vendors like SiFive, STMicroelectronics, Silicon Labs, NXP, Xilinx, NVIDIA and others.
In a series of joint webinars with Microchip throughout the year, as well as our own blog notes, we mostly focused on the interactive use cases of Renode for hardware/software co-development.
But the collaborative nature of virtual development - with features such as state saving, event storing/replaying, synchronous debug of multi-node environments and simply being able to share your work with colleagues using a bunch of files - is best experienced in a cloud environment, where resources can be truly shared and easily scaled. Renode Cloud Environment is an open source design, testing and CI system that builds on and integrates with Renode. Come by and see how this can work to your advantage.
This will also be a chance to learn about recent developments in version 1.8 such as physical FPGA and Verilator co-simulation, enhanced multi-core debug, support for many new RISC-V and other platforms.
Python-based open source USB test suite with Cocotb
CHIPS Alliance is an exciting new initiative driving fully open source, high quality IP and tooling for ASIC design.
As an active Gold Member, Antmicro will also be present at the CHIPS Alliance booth - demoing our “Python-based open source USB test suite with Cocotb”. The open source USB IP cores test suite developed by Antmicro is used to test various open source USB IP for compliance to USB spec and real-world usage. Based on Cocotb, it allows for easy test design and use of large library of Python modules for an entirely open source, software-centric test & verification flow. The test suite is now available on GitHub. Read the full blog note (linked to above) for all the details.
Fomu: Python, RISC-V, and FPGA in your USB Port
On Thursday December 12th join us at 9:00 am for a tutorial in partnership with Google, Fomu: Python, RISC-V, and FPGA in your USB Port, co-presented by Google’s Tim ‘mithro’ Ansell and Antmicro’s Michael Gielda, in Grand Ballroom 220-C.
As the abstract reads, “The tutorial will give the audience hands-on experience with customizing a fully open source RISC-V design running the Zephyr RTOS in a tiny FPGA that fits in your computer’s USB port (Fomu - FPGA Open Micro USB) - an ultimately portable RISC-V development environment. […] After the tutorial, the participants will walk away not only with a Fomu board, but also with practical knowledge of how to work with a real FPGA RISC-V design effectively and how to modify it to their own needs.”
Taking open digital design to the next level
Big announcements from Antmicro are to be expected, with the company’s steady movement towards a consequent and complete offering of truly open digital design services. In partnership with zGlue, a bold startup aiming to drastically reduce the cost of designing custom chips, we will be presenting new ways for making this goal a reality in the RISC-V community and beyond.
If you would like to schedule a meeting at the booth to discuss project opportunities and learn more, don’t hesitate to write to firstname.lastname@example.org. The engineering team on site will be more than happy to answer your questions.