With very broad support for simulating RISC-V, Armv8-R and Armv8-A platforms, Renode is addressing the need to target scenarios of increasing complexity, including multi-core, heterogeneous embedded systems or server applications for management, security...
To streamline Antmicro’s wide-ranging embedded product development work for customers in aerospace, medical, automotive and other areas, we have been building a portfolio of reference designs and making it available on our open hardware portal. Together...
ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. Taking advantage of this modularity and enabling automation and reuse of blocks across designs requires tools for automated processing and generation of top...
The complexity of the multi-stage ASIC design process is reflected in the structure of the most popular open source project in this space called OpenROAD which offers a collection of ASIC design tools that can be put together into a complete ASIC flow in...
Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer can put constraints in place...
Antmicro has created a broad portfolio of open source hardware designs that constitute a perfect entry point for product development, as showcased on our Open Hardware Portal. Since a lot of our projects focus on complex applications such as video processing