OPEN SOURCE TOOLS, OPEN FPGA, OPEN ISA
OPEN SOURCE TOOLS, OPEN FPGA, OPEN ISA

BOOSTING MACHINE LEARNING WITH TAILORED ACCELERATORS: CUSTOM FUNCTION UNITS IN RENODE

Published:

CFU in Renode diagram

Development of Machine Learning algorithms which enable new and exciting applications is progressing at a breakneck pace, and - given the long turnaround time of hardware development - the designers of dedicated hardware accelerators are struggling to keep...

OPEN SOURCE TOOLS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN FPGA

ADVANCED CO-SIMULATION WITH RENODE AND VERILATOR: ZYNQ AND FASTVDMA

Published:

Diagram depicting co-simulation of Zynq

Co-simulation is extremely useful for developing complex systems, especially those targeting FPGA SoCs, where specialized IP cores often interact with advanced software running on the hard CPU. Co-simulation has been available in Renode for quite a while...

OPEN FPGA, OPEN SOURCE TOOLS, OPEN ISA
OPEN FPGA, OPEN SOURCE TOOLS, OPEN ISA

LEON3 SUPPORT IN RENODE

Published:

LEON3 and Renode logos

Over the many years of development, Renode, our open source simulation framework, has been successfully used in various contexts, from the development on the smallest microcontrollers to complex, multi-core and multi-node environments, from driver implementation...

OPEN SOURCE TOOLS, OPEN FPGA, OPEN ASICS, OPEN CLOUD SYSTEMS
OPEN SOURCE TOOLS, OPEN FPGA, OPEN ASICS

AUTOMATIC SYSTEMVERILOG LINTING IN GITHUB ACTIONS WITH VERIBLE

Published:

Diagram depicting Verible integration with Github Actions

With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter is a static code analysis tool that has been helping us and our collaborators to...

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