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asic

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

IMPLEMENTING AUTOMATIC CLOCK GATING IN THE OPENROAD ASIC DESIGN TOOLCHAIN

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Clock gating animation Reducing power usage is a major aspect of chip design, important especially for energy-efficient systems and battery-powered devices. A significant amount of the power used by a typical chip is consumed by gate switching, and...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

POWER ESTIMATION IN OPENROAD USING SAIF IN VERILATOR

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Power estimation with Verilator and OpenROAD Power consumption is a major aspect of chip design, and the ability to reliably and efficiently predict it can save a lot of engineering cycles. While it is difficult to predict the exact consumption upfront without delving...
OPEN ASICS, OPEN FPGA, OPEN SOURCE TOOLS

AUTOMATING DIGITAL DESIGN AND VERIFICATION TRACKING WITH TESTPLANNER

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Testplanner illustration In digital design, ensuring systematic verification of all design aspects requires not only proper planning of design verification and test development, but also tools to track and make sure that design development and verification...
OPEN HARDWARE, OPEN ASICS

INTRODUCING ANTMICRO’S OPEN SOURCE MYRA SYSTEM-IN-PACKAGE

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Photo of the Myra SiP and baseboard System-in-Packages (SiP) are a way of enclosing multiple integrated circuits into a single component package, often used in space-constrained consumer applications like in wearables or cell phones or miniaturized, environment...
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