Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
The OpenROAD project provides an open source ASIC toolchain that reduces the entry barriers to the field of hardware development and allows fast-turnaround feedback about your design, helping increase productivity of silicon...
Among other things, Antmicro’s work towards improving the vertical integration potential of customers designing ASIC solutions often sees us enhance one of the flagship open source projects in this space, Verilator, which complements...
Leading the efforts of the Tools Workgroup in CHIPS Alliance, across a variety of customer projects, as well as own R&D, at Antmicro we are actively looking for and capturing the productivity enhancements that can be achieved...
Digital circuits are becoming more and more complicated due to constant technology development and increasing user expectations. In response to this growing complexity, development tools that provide a higher level of abstraction...
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