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OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INITIAL ASSERTION CONTROL SUPPORT IN VERILATOR

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Initial assertion control support in Verilator Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

ADDING PHYSICAL MEMORY PROTECTION TO THE VEER EL2 RISC-V CORE

Published:

PMP for VeeR EL2 - graphical interpretation Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code...
OPEN SOURCE TOOLS, OPEN ASICS

INITIAL OPEN SOURCE SUPPORT FOR UVM TESTBENCHES IN VERILATOR

Published:

Running simple UVM testbenches in Verilator Leading the efforts of the Tools Workgroup in CHIPS Alliance, across a variety of customer projects, as well as own R&D, at Antmicro we are actively looking for and capturing the productivity enhancements that can be achieved...
OPEN FPGA, OPEN SOURCE TOOLS

FULLY OPEN SOURCE FPGA DESIGN FOR SDI-MIPI VIDEO CONVERTER

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Fully open source FPGA design for SDI-MIPI Video Converter illustration SDI is a popular industrial camera standard used in video broadcast, supporting transmission over a single coaxial cable. But embedded SoCs used in drone, robotics and IoT applications typically only support MIPI CSI-2 natively...
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