With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter is a static code analysis tool that has been helping...
OPEN SOURCE TOOLS, OPEN FPGA, OPEN ASICS, OPEN ISA
Open source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open ISA and ecosystem, in which Antmicro participated...
UVM is a verification methodology traditionally used in chip design which has historically been missing from the open source landscape of verification-focused tooling. While new, open source approaches to verification have...
We are excited to announce the ARVSOM - Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71x0 SoC. Using the RISC-V architecture, which Antmicro has been heavily involved in since the early...
Originally issued by CHIPS Alliance
CHIPS Alliance continues to grow with more than 25 companies collaborating on open source hardware and software technologies
SAN FRANCISCO, Feb. 11, 2021 – CHIPS Alliance, the leading...
In our daily work at Antmicro we use FPGAs primarily for their flexibility and parallel data processing capabilities that make them remarkably effective in advanced vision and audio processing systems involving high-speed interfaces...
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