Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for executable code and digital design...
A few years back Antmicro introduced the first DDR5 capable platform to our open source FPGA-based Rowhammer research framework developed in cooperation with Google - the Data Center RDIMM DDR5 Tester. The follow-on SO-DIMM...
The Caliptra Root of Trust project, a collaboration between AMD, Google, Microsoft and NVIDIA within the CHIPS Alliance, is steadily heading towards its 2.0 release – an effort Antmicro is actively contributing to. We’ve recently...
In recent years Antmicro has been working for customers within the CHIPS Alliance’s Caliptra Workgroup, led by AMD, Google, Microsoft and NVIDIA, to maintain and gradually enhance the RISC-V VeeR EL2 CPU core that is used in...
Asymmetric multiprocessing (AMP) setups are very common in modern SoCs which mix various types of cores or even architectures to provide sufficient processing power when needed, while keeping the system energy efficient overall...
ASIC and FPGA designs consist of distinct blocks of logic bound together by a top-level design. Taking advantage of this modularity and enabling automation and reuse of blocks across designs requires tools for automated processing...
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