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In digital design, ensuring systematic verification of all design aspects requires not only proper planning of design verification and test development, but also tools to track and make sure that design development and verification...
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Antmicro has been providing engineering support for Verilator in a variety of ASIC-related projects, which often include complex, state-of-the-art designs and take a lot of time time and memory to run. Normally, when generating...
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When developing complex FPGA designs and custom SoCs, simulating and testing HDL designs in a larger context is necessary to accurately replicate real use cases. For fast iteration, you can combine cycle-accurate RTL simulation...
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In a long-running collaboration with Google, Antmicro has been working on demonstrating how the XLS Mid-Level Synthesis toolchain can be used to increase productivity of developing highly parallel ASIC solutions.
The initial...
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Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for executable code and digital design...
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A few years back Antmicro introduced the first DDR5 capable platform to our open source FPGA-based Rowhammer research framework developed in cooperation with Google - the Data Center RDIMM DDR5 Tester. The follow-on SO-DIMM...
