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OPEN SOURCE SYSTEM ON MODULE WITH MICROCHIP POLARFIRE SOC

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Photo of the PolarFire SoM The PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks to the ongoing collaboration...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INITIAL ASSERTION CONTROL SUPPORT IN VERILATOR

Published:

Initial assertion control support in Verilator Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

INTRODUCING CONSTRAINED RANDOMIZATION IN VERILATOR

Published:

Constrained randomization in Verilator illustration Large and complex SystemVerilog designs, such as CPUs, are difficult to test thoroughly, as there are many interesting signal combinations that influence a design’s behavior, including corner cases that are easy to overlook...
OPEN SOURCE TOOLS, OPEN ISA

DEVELOPING AND TESTING HETEROGENEOUS SPACE SYSTEMS WITH RENODE

Published:

Renode for space - main illustration While landing humans on the Moon was a feat accomplished with very basic compute power of 2MHz provided by the Apollo Guidance Computer, modern spacecraft can take advantage of a much more advanced and capable data processing...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

ADDING PHYSICAL MEMORY PROTECTION TO THE VEER EL2 RISC-V CORE

Published:

PMP for VeeR EL2 - graphical interpretation Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code...
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