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Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of...
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In recent years Antmicro has been working for customers within the CHIPS Alliance’s Caliptra Workgroup, led by AMD, Google, Microsoft and NVIDIA, to maintain and gradually enhance the RISC-V VeeR EL2 CPU core that is used in...
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Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
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As the complexity of space-faring hardware and software increases, so does the significance of extensive automated testing, traceability and a dependable, collaborative development environment. During the International Conference...
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The PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks to the ongoing collaboration...
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The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger systems, standalone embedded MCUs and even many-core server AI processing solutions
