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OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

ADDING PHYSICAL MEMORY PROTECTION TO THE VEER EL2 RISC-V CORE

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PMP for VeeR EL2 - graphical interpretation Antmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure including code quality checks, code...
OPEN ISA, OPEN SOURCE TOOLS

EXPANDING RISC-V SUPPORT IN RENODE WITH BIT-MANIPULATION EXTENSIONS

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RISC-V bitmanip support in Renode illustration Antmicro’s open source Renode simulation framework offers support for various instruction set architectures, with the RISC-V ISA being a major focus for both ourselves – as a founding member of RISC-V International – and our...
OPEN SOURCE TOOLS, OPEN OS

EXPANDING RENODE PLATFORM COVERAGE WITH THE U-BOOT DASHBOARD

Published:

Renode U-Boot dashboard illustration With the rapid uptick in the adoption of our Renode open source embedded system simulation framework in areas like automotive and space, Antmicro has been steadily expanding support for new hardware targets, most recently
OPEN SOURCE TOOLS, OPEN SOFTWARE LIBRARIES

PYTHON-DRIVEN AUTOMATION AND SCRIPTING IN RENODE WITH PYRENODE3

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pyrenode3 illustration A user-friendly, well-structured Command Line Interface (CLI) is especially critical in software development tools used for scripting, automation and CI. With our open source Renode simulation framework, Antmicro helps product...
OPEN SOURCE TOOLS, EDGE AI, OPEN ASICS

ENABLING SECURE OPEN SOURCE ML PRODUCTS WITH OPEN SE CURA

Published:

Open Se Cura illustration Today at the RISC-V Summit in Santa Clara, we’re pleased to participate in Google’s announcement of the open source release of project Open Se Cura. The announcement crowns a many-year collaboration towards developing a secure...
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