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simulation

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OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

CPU RTL CO-SIMULATION IN RENODE

Published:

CPU RTL co-simulation in Renode Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to cover ASIC and FPGA SoC development...
OPEN SOURCE TOOLS, OPEN ASICS

PROGRESS IN OPEN SOURCE SYSTEMVERILOG / UVM SUPPORT IN VERILATOR

Published:

Verilator and UVM illustration Verilator is a shining example of a widely-accepted open source tool which provides state-of-the-art results in the ASIC design space. It is commonly used for simulation and testing, but originally, due to the lack of capability...
OPEN SOURCE TOOLS, OPEN SIMULATION

PROVIDING SYNCHRONIZED MULTI-SENSOR DATA IN RENODE WITH RESD

Published:

Synchronized multi-sensor data in Renode with RESD When deploying consumer-facing products which process multi-sensor data in the field it’s almost impossible to predict all possible scenarios. But massively scalable, reliable and deterministic testing in simulation can get...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

SCALING VERILATOR FOR VERY LARGE DESIGNS

Published:

Improving Verilator illustration Verilator is a fast, open source simulator widely used in the ASIC and FPGA ecosystem, offering state-of-the-art (or better) results in contexts otherwise dominated by proprietary offerings. Its open source nature and the promise...
OPEN NETWORKING, OPEN OS, OPEN SOURCE TOOLS

BLUETOOTH MESH NETWORKING PATHFINDING ALGORITHM DEVELOPMENT USING RENODE

Published:

Distributed system map Antmicro’s open source Renode simulation framework offers support for the Bluetooth Low Energy (BLE) protocol and multi-node simulation capabilities, which makes it a great environment for development, debugging and testing...
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