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simulation

OPEN SOURCE TOOLS, OPEN ASICS

INITIAL OPEN SOURCE SUPPORT FOR UVM TESTBENCHES IN VERILATOR

Published:

Running simple UVM testbenches in Verilator Leading the efforts of the Tools Workgroup in CHIPS Alliance, across a variety of customer projects, as well as own R&D, at Antmicro we are actively looking for and capturing the productivity enhancements that can be achieved...
OPEN SOURCE TOOLS

FUZZING ZEPHYR WITH AFL AND RENODE

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Fuzzing Zephyr with AFL and Renode illustration Fuzzing is an automated testing technique aimed at detecting problems like crashes or memory leaks in software by feeding it with invalid, often random input. It is especially valuable in safety-critical use cases, e.g. in...
OPEN SOURCE TOOLS, OPEN OS, OPEN ISA

RENODE 1.14 WITH ARMV8 SUPPORT, IMPROVED CO-SIMULATION AND NEW PLATFORMS

Published:

Renode 1.14 illustration Antmicro is happy to announce the next, 1.14 release of our open source Renode simulation framework, including lots of new developments originating from both customer and R&D projects, along with community contributions. Since...
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

DPI SUPPORT IN RENODE FOR HDL CO-SIMULATION WITH VERILATOR AND QUESTA

Published:

DPI support in Renode for HDL co-simulation Hardware Description Languages (HDLs), such as Verilog and SystemVerilog, are used to express the behavior of digital electronic circuits for field-programmable gate arrays (FPGAs) and application-specific integrated circuits...
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