Published:
Antmicro has been providing engineering support for Verilator in a variety of ASIC-related projects, which often include complex, state-of-the-art designs and take a lot of time time and memory to run. Normally, when generating...
Published:
When developing complex FPGA designs and custom SoCs, simulating and testing HDL designs in a larger context is necessary to accurately replicate real use cases. For fast iteration, you can combine cycle-accurate RTL simulation...
Published:
The growing complexity of the hardware Antmicro helps its customers build and deploy software workloads on requires continuous benchmarking and optimization to track, understand and fix performance bottlenecks. In our work...
Published:
Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for executable code and digital design...
Published:
SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable...
Published:
While helping customers automate and optimize their workflows, especially in complex use cases like ASIC design, Antmicro often finds itself building and enhancing multi-layered code generation infrastructure, HLS tools, transpilers...
