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systemverilog

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

IMPLEMENTING AUTOMATIC CLOCK GATING IN THE OPENROAD ASIC DESIGN TOOLCHAIN

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Clock gating animation Reducing power usage is a major aspect of chip design, important especially for energy-efficient systems and battery-powered devices. A significant amount of the power used by a typical chip is consumed by gate switching, and...
OPEN SOURCE TOOLS

AUTOMATED AND STANDARDIZED SOFTWARE BENCHMARKING WITH BENCHALOT

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Benchalot illustration The growing complexity of the hardware Antmicro helps its customers build and deploy software workloads on requires continuous benchmarking and optimization to track, understand and fix performance bottlenecks. In our work...
OPEN SOURCE TOOLS, OPEN SIMULATION

GENERATING INTERACTIVE COVERAGE DASHBOARDS WITH COVERVIEW

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Coverview illustration Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for executable code and digital design...
OPEN SOURCE TOOLS, OPEN SIMULATION

SIMPLIFYING RENODE MODEL GENERATION WITH SYSTEMRDL-TO-C# CONVERSION

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SystemRDL support in Renode illustration SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable...
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