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While helping customers automate and optimize their workflows, especially in complex use cases like ASIC design, Antmicro often finds itself building and enhancing multi-layered code generation infrastructure, HLS tools, transpilers...
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Debugging and extending ASIC and FPGA tools such as RTL simulators often means digging through vast codebases of not only the tooling itself but the designs they take as input. This can be cumbersome, especially in the context...
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Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
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Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
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Large and complex SystemVerilog designs, such as CPUs, are difficult to test thoroughly, as there are many interesting signal combinations that influence a design’s behavior, including corner cases that are easy to overlook...
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Among other things, Antmicro’s work towards improving the vertical integration potential of customers designing ASIC solutions often sees us enhance one of the flagship open source projects in this space, Verilator, which complements...
