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Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for executable code and digital design...
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SystemRDL is a standard from the Accelera initiative used to describe the register layout of hardware in order to provide a single source of truth for hardware and software artifacts. As a single, human-writeable and readable...
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While helping customers automate and optimize their workflows, especially in complex use cases like ASIC design, Antmicro often finds itself building and enhancing multi-layered code generation infrastructure, HLS tools, transpilers...
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Debugging and extending ASIC and FPGA tools such as RTL simulators often means digging through vast codebases of not only the tooling itself but the designs they take as input. This can be cumbersome, especially in the context...
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Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
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Antmicro is continuously working on improving productivity of ASIC design and verification workflows using open source tools as leaders of the CHIPS Alliance Tools Workgroup, as well as for customer and R&D projects. Extending...
