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Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
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Large and complex SystemVerilog designs, such as CPUs, are difficult to test thoroughly, as there are many interesting signal combinations that influence a design’s behavior, including corner cases that are easy to overlook...
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One of the key metrics helping ensure code quality is test coverage, providing objective, automatic ways of making sure that all of the most important branches of the code are verified. Antmicro’s open source Renode simulation...
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Antmicro’s open source Renode simulation framework offers support for various instruction set architectures, with the RISC-V ISA being a major focus for both ourselves – as a founding member of RISC-V International – and our...
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A user-friendly, well-structured Command Line Interface (CLI) is especially critical in software development tools used for scripting, automation and CI. With our open source Renode simulation framework, Antmicro helps product...
