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Code coverage is a useful metric to keep track of while developing test suites, providing engineering teams with an actionable overview of how broad their testing goes. This is true both for executable code and digital design...
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While helping customers automate and optimize their workflows, especially in complex use cases like ASIC design, Antmicro often finds itself building and enhancing multi-layered code generation infrastructure, HLS tools, transpilers...
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The Caliptra Root of Trust project, a collaboration between AMD, Google, Microsoft and NVIDIA within the CHIPS Alliance, is steadily heading towards its 2.0 release – an effort Antmicro is actively contributing to. We’ve recently...
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Debugging and extending ASIC and FPGA tools such as RTL simulators often means digging through vast codebases of not only the tooling itself but the designs they take as input. This can be cumbersome, especially in the context...
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Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of...
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Digital design verification often utilizes the so-called constrained randomization functionality offered by SystemVerilog, where in order to efficiently test designs with random but still correct data, a digital logic designer...
