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Universal Verification Methodology (UVM) is one of the most popular verification methods in digital design, focusing on standardization and reusability of verification IP and environments. For the last few years, Antmicro has...
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Monitoring code coverage in digital design projects requires tracking both traditional software metrics such as executed code lines and visited branches, as well as more use-case specific concepts such as bit field toggles...
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Power consumption is a major aspect of chip design, and the ability to reliably and efficiently predict it can save a lot of engineering cycles. While it is difficult to predict the exact consumption upfront without delving...
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Antmicro has been providing engineering support for Verilator in a variety of ASIC-related projects, which often include complex, state-of-the-art designs and take a lot of time time and memory to run. Normally, when generating...
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When developing complex FPGA designs and custom SoCs, simulating and testing HDL designs in a larger context is necessary to accurately replicate real use cases. For fast iteration, you can combine cycle-accurate RTL simulation...
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The growing complexity of the hardware Antmicro helps its customers build and deploy software workloads on requires continuous benchmarking and optimization to track, understand and fix performance bottlenecks. In our work...
