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UVM is a verification methodology traditionally used in chip design which has historically been missing from the open source landscape of verification-focused tooling. While new, open source approaches to verification have...
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Throughout 2020 we have been hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe...
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Antmicro’s open source work spans all parts of the computing stack, from software and AI, to PCBs, FPGAs and, most recently, custom silicon. We connect those areas with an overarching vision of open source tooling and methodology...
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At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools.
Verilog, SystemVerilog and open tooling
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Antmicro’s open source simulation framework, Renode, was built to enable simulating real-life scenarios - which have a tendency to be complex and require hybrid approaches.
That’s why, besides other things, the Renode 1.7...
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Cocotb
One of the great open source tools in our arsenal that we’ve grown very fond of throughout the years is Cocotb, a very clever framework for simulating HDL (VHDL, Verilog or SystemVerilog) designs. Cocotb is maintained...
