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Verilator is a fast, open source simulator widely used in the ASIC and FPGA ecosystem, offering state-of-the-art (or better) results in contexts otherwise dominated by proprietary offerings. Its open source nature and the promise...
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Antmicro uses open source to introduce pragmatic innovation into areas which have traditionally been heavily reliant on proprietary technologies such as ASIC and FPGA. Due to high complexity and long design cycles, testing...
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At Antmicro we strongly believe that open source flows are key to bringing software-driven innovation into the ASIC space, in order to build a collaborative ecosystem and scalable, reproducible and publicly available components...
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Verilator is a popular open source SystemVerilog simulator and one of the key tools in the ASIC and FPGA ecosystem, which Antmicro is actively using and developing, e.g. by enabling co-simulation with Renode or Cocotb integration
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Development of Machine Learning algorithms which enable new and exciting applications is progressing at a breakneck pace, and - given the long turnaround time of hardware development - the designers of dedicated hardware accelerators...
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With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter is a static code analysis tool that has been helping...
