Open source FPGA tools and Renode support for Core-V MCU

For over a year now we have been working together with QuickLogic towards supporting their FPGA devices in open source FPGA tooling. This is the first time in history where an FPGA vendor has gotten directly involved in enabling a fully open flow for its products. The ease of adapting the internal operation of FPGAs to specific needs perfectly resonates with the dynamically changing landscape of Machine Learning (ML) where other platforms can’t provide the required design freedom, and open source FPGA tooling is key to enabling new workflows that will fully capitalize on this potential.

QuickLogic and Antmicro’s commitment to open source ML does not end there. To enable total design freedom, QuickLogic and Antmicro are now collaborating to build open source simulation (Renode), hardware (QuickFeather) and software (Zephyr) for QuickLogic’s Arm-based EOS S3 FPGA SoC platform to bolster the emerging ecosystem of FPGA-enhanced TinyML.

Now we are taking yet another step in the collaboration - in a joint project with Google and QuickLogic we are developing Renode simulation and open source FPGA tooling support for OpenHW Group’s exciting Core-V MCU project featuring the CV32E40P RISC-V core alongside QuickLogic’s eFPGA fabric. Building on the open source RISC-V ISA and with an open source FPGA inside, it will be an extremely capable and flexible target for TinyML applications. It is available for pre-silicon development thanks to support from Renode, which includes FPGA co-simulation capability.

We recently discussed those and other developments in the open source TinyML space in a keynote panel discussion with Google’s Tim Ansell, Zephyr Project’s Kate Stewart and QuickLogic’s Brian Faith at the RISC-V Summit, which Antmicro had the privilege to moderate.

Democratizing hardware design

In the broader ecosystem of the CHIPS Alliance that Antmicro, QuickLogic and Google are members of, the open FPGA toolchain is part of a wider effort aimed at enabling vendor-neutral and collaborative approach to ASIC and FPGA design. CHIPS also includes projects such as OpenROAD, constituting a fully open ASIC design tool flow, or the groundbreaking SkyWater PDK project that resulted in the first ever open source release of a process design kit for fabrication of integrated circuits. Spearheading many of CHIPS’ activities in the tools space, we are looking at ML-assisted and collaborative, CI-driven flows for ASIC and FPGA design enabled by open source that will be the future of the industry. With both Renode and open FPGA tooling focusing on bringing the hardware and software worlds closer together, this is yet another building block in a vision shared by Antmicro, QuickLogic, Google and our CHIPS partners like Western Digital, efabless and others.

Open source friendly eFPGA fabric, anyone?

Supporting open source FPGA tools makes perfect sense, especially for QuickLogic, which specializes in low power SoCs that embed eFPGAs, as well offers those same eFPGA fabrics for licensing to other entities. And these licensees may very likely be thrilled about the concept of having the eFPGA cores and SoCs that integrate them to be fully supported by an open source, vendor-agnostic toolchain.

The adoption of open source tools has greatly increased the appeal for QuickLogic’s eFPGA fabric in new TinyML products, as the relevant toolchain can now be provided openly via GitHub, without licensing restrictions, in a developer-friendly way. QuickLogic’s involvement with FPGA SoC technologies, combining the fabric with hard CPUs, and combining open tools with open RTOS, drivers, hardware and simulation tools, also brings the play closer to open source minded software developers, who play a central role in real-world machine learning applications.

Core-V is not QuickLogic’s first foray into RISC-V territory: their eFPGA has already been featured in the experimental Arnold project done with ETH Zurich in 2018, where it was combined with the low-power RISC-V PULPissimo core that is the predecessor of CV32E40P. Now, a new generation of the eFPGA fabric is going to be used in the upgraded Core-V MCU, offering significant processing power for small ML applications requiring real-time processing capabilities.

Renode for rapid Machine Learning development

Google’s involvement in this open FPGA tooling and Renode support project is related to their interest in new, open source driven and FPGA enhanced TinyML that may be the future of this fast-changing space thanks to its extreme flexibility. On top of the Core-V support, in collaboration with the TensorFlow Lite for Microcontrollers team, Renode is now being adopted in the official CI for TF Lite Micro. Renode’s hardware-software co-design capabilities as well as recently added metrics recording, analysis and sharing capabilities are also key to a more data-driven approach to TinyML that Google wants to promote.

In this project, which has grown to an extensive collaboration between Antmicro and Google, we are working towards enabling continuous testing of TensorFlow Lite Micro on a variety of platforms, including the sensor-packed Arduino Nano 33 BLE Sense featuring Nordic’s nRF52840. To enable the testing of various TF Lite Micro demos, Renode’s capabilities have been extended with new video and sound processing features, and we’ve made it even easier for new users to start developing using Renode by enabling deployment of binaries directly from the Arduino IDE and Arduino CLI via the new integration layer.

RISC-V + FPGA

The Core-V MCU is an excellent showcase of how the openness and design freedom allowed by the RISC-V ISA can be enhanced with an open source capable FPGA and a software driven workflow using Renode.

If you are building a next-generation machine-learning capable product and are interested in using RISC-V and/or FPGAs as your primary platform, follow this development and reach out to us to find out what services and tools we can provide you with to get you going faster.