Cortex-R support in Renode for safety-critical applications


Topics: Open source tools, Open OS

To cover the widest possible range of complex embedded systems, Renode offers broad architecture and platform support, with ARM being a crucial part of that ecosystem. Following the important milestone of adding support for 64-bit ARMv8-A in Renode described in a recent blog note, we are now happy to announce support for the 32-bit ARM Cortex-R52 CPU, expanding our simulation framework’s capabilities to new use cases requiring real-time and reliable processing.

Cortex-R52, the first ARMv8-R processor to be added to Renode, offers high performance 32-bit processing, suitable for advanced real-time embedded systems, especially in safety-critical fields such as aerospace, automotive and medical or industrial robots. It is implemented in MCUs such as Renesas RZ/T2M and NXP S32Z and S32E, targeted at verticals requiring real-time processing and enhanced security.

Cortex-R52 uses two instruction sets: A32 (Arm) and T32 (Thumb), the latter introducing 32-bit instructions that are intermixed with the 16-bit instructions. With security playing a critical role in the ARM R-Profile, R52 offers several features for enhanced safety, including software separation, a bare metal hypervisor for hardware virtualization and a Memory Protection Unit (MPU).
Adding initial support for Cortex-R52 will also open up the way to enabling a new family of platforms in our Zephyr and U-Boot dashboards which use Renode to test the respective OS and bootloader at scale.

ARMv8-R in Renode illustration

Implementing support for Cortex-R52 in Renode

The work was based on the recently announced Renode support for ARMv8 and used the Zephyr RTOS to drive the implementation and regression testing.

The cortex-r52.repl platform file now included in mainline Renode describes a simple system with ARM Cortex-R52, GIC, Generic Timer, PL011 UART and memory. Zephyr provides a generic Cortex-R52 platform called fvp_baser_aemv8r_aarch32 which contains three functional blocks, as reflected in the REPL sample above. This platform was used as a basis for Zephyr testing of R52 implementation in Renode.

Implementing the initial Cortex-R52 support required several improvements in Renode’s translation library (tlib), namely:

  • adding support for A32 and T32 instructions sets
  • adding interrupt support for 32-bit ARMv8
  • adding AArch32 system registers
  • adding MPU support

To validate the Cortex-R52 implementation in Renode we used the ARMv8R Robot test which includes an interesting set of custom Robot Framework keywords created for this purpose.

Cortex-R52 demo in Renode

You can use Renode’s built-in Cortex-R52 script to test Cortex-R52 simulation on your local machine:

include @scripts/single-node/cortex-r52.resc

The script loads the Cortex-R52 platform file and runs the Zephyr philosophers demo.

You can also run a custom payload by providing a path to your binary before running the above script:

set bin @/home/user/firmware.elf
include @scripts/single-node/cortex-r52.resc

Renode for real-time and safety-critical systems development

Cortex-R52 support in Renode is being actively developed, with more features underway, including hypervisor support. Developments described in this note, driven by a customer project, help bring Renode to more use cases, especially in timing sensitive and safety-critical environments such as aerospace and automotive applications, and lay the foundation for expanding support to other Cortex-R chips and peripherals in the future.

If you’re interested in expanding Cortex-R support in Renode or integrating Renode in your embedded product development process, reach out to us at

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