Fully open source FPGA design for SDI-MIPI Video Converter
Topics: Open FPGA, Open source tools
SDI is a popular industrial camera standard used in video broadcast, supporting transmission over a single coaxial cable. But embedded SoCs used in drone, robotics and IoT applications typically only support MIPI CSI-2 natively, and so SDI to MIPI CSI-2 is necessary in order to bridge the two worlds together. This can drive new applications where legacy SDI-based video setups can be enhanced with embedded AI processing using Antmicro’s broad range of MIPI CSI-2 capable open hardware platforms like the popular Jetson Orin Baseboard.
This was the motivation for Antmicro’s original SDI to MIPI CSI-2 Bridge which was followed by the more powerful, Lattice CrossLink-NX based SDI-MIPI Video Converter. As a part of a recent R&D effort, we implemented an FPGA design for the SDI-MIPI Video Converter with a new, fully open source FPGA core that we will describe in this note along with the benefits brought by moving to an end-to-end open source design flow.
Next generation SDI-MIPI converter
The next-gen version of the SDI-MIPI converter uses a newer, more powerful CrossLink-NX FPGA which contains 6.5 times more logic cells (39k vs. 5.9k) and provides an additional soft D-PHY interface.
The PCB design of the new board is open source and available on Antmicro’s Open Hardware Portal, which allows for all kinds of customizations as well as integration into larger designs which Antmicro can perform for you. You can learn more about the board and the FPGA design and their capabilities in the project’s documentation.
The first version of the SDI-MIPI board used an FPGA design based on a proprietary CMOS2DPHY IP core for converting and transmitting parallelized data in the MIPI CSI-2 standard, as described in more detail in a separate blog note. The FPGA used on the newer board, CrossLink NX, is supported in open source FPGA toolchains, and so using proprietary cores - tied to the tools that generate them - would not let us benefit from the flexibility of a completely open source approach. Thus, for the new board we implemented a fully open source design that’s synthesizable with open source tools, which grants us total control over the entire flow, from HDL source to bitstream.
SDI to MIPI CSI-2 Video Converter FPGA design
The CMOS to D-PHY FPGA core developed by Antmicro for this project allows you to convert a parallel signal to a MIPI CSI-2 signal. The serial SDI signal goes into a deserializer which converts it to a parallel signal with additional synchronization lanes. This is then passed to the Lattice Crosslink-NX FPGA, which converts it to the MIPI CSI-2 protocol.
The CMOS to D-PHY converter is capable of generating MIPI CSI-2 packets and switching MIPI D-PHY link modes. It consists of the following modules:
- Packet Formatter (Low Level Protocol) - a MIPI CSI-2 packet generator that generates SoT (Start of Transmission), EoT (End of Transmission), a header and a footer for each packet.
- Checksum generator - a combinatorial 16-bit CRC checksum generator.
- TX Global Operations - controls the D-PHY interface lanes switching between Low Power (LP) and High Speed (HS) modes.
- CSI-2 Finite State Machine - not strictly a part of the MIPI CSI-2 protocol, it controls the MIPI CSI-2 protocol flow. The FSM synchronizes to the beginning of the frame and then initiates D-PHY packet transfers while controlling the Packet Formatter and the TX Global Operations modules.
- Hardened TX D-PHY - the MIPI D-PHY interface provided by the FPGA fabric, configured to operate as a transmitter, controlled by TX Global Operations.
For detailed instructions on building and loading the bitstream, refer to the project’s README.
With an open source FPGA design you have more flexibility and control over tools used during development, enabling e.g. in-depth end-to-end testing of your designs without juggling licenses. For example, we used cocotb and Verilator to create a completely open verification suite for our core. The developed unit tests are responsible for checking whether all signals are in their expected states and whether the implemented protocol works as desired. To automate the build and verification process of this project we developed a CI pipeline for building the bitstreams and another one for simulating a behavioral model of the design in Verilator and testing it in cocotb.
Design open source FPGA cores with Antmicro
Using open source FPGA cores such as the one described in this note allows you to benefit from a variety of open source tools that can provide you with more flexibility and control over the FPGA design process without license limitations.
Antmicro offers a wide range of FPGA, software, and hardware development services to help you develop FPGA-based devices tailored to your needs. We can help integrate open source tools into your workflow for vendor-neutral and software-driven FPGA development. Our experience spans multiple sectors, industries, and projects at all stages of development. If you are interested in developing your next FPGA project with Antmicro, reach out to us at firstname.lastname@example.org.