Enabling open source UVM verification of AXI-based systems in Verilator

Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of nearly every imaginable feature of SystemVerilog that the Language Reference Manual (the IEEE 1800-2023 standard) allows, which had so far been a problem for open source simulation tooling.

Last year, we announced Antmicro’s success with creating simple UVM testbenches running in Verilator. In the months that followed, we built on this further by introducing constrained randomization using SMT solvers and continuing to add missing features needed for UVM. The work, carried out within the framework of the CHIPS Alliance and supported with the EU-funded TRISTAN research project, was always aimed at enabling practical use with real-world UVM VIPs, as presented in the current article.

With a range of further enhancements to Verilator, such as support for clocking blocks in virtual interfaces and inline random variable control alongside numerous bugfixes, mostly aimed at further improving randomization, Verilator can now simulate axi-vip, a UVM-based open source VIP for AXI (Advanced eXtensible Interface) bus implementations. As an open standard and one of the prevalent memory buses in ARM SoCs, AXI is widespread in the industry, also finding use in RISC-V based designs such as Caliptra 2.0, where the VIP will be used to enable end-to-end open source verification of the platform’s redesigned system bus interfaces.

A standardized, open source verification flow for Caliptra 2.0

axi-vip is built on top of UVM and provides the necessary components for modeling interactions with AXI buses and monitoring their activity. By providing support for axi-vip in Verilator, we have taken a large step towards the goal of creating open source support for SystemVerilog UVM testbenches in Verilator, building on the previous work mentioned above.

The AXI bus is intended to be used in the RISC-V-based VeeR core as an alternative to AHB used in the 2.0 version of the Caliptra Root of Trust project led by AMD, Google, Microsoft and NVIDIA. As part of enabling AXI support in Caliptra, Antmicro has been customizing the VeeR EL2 core further, building on its existing support for AXI.

One of the changes in the Caliptra 2.0 specification is the introduction of the MCU subsystem, which is responsible for the boot flow. As we have now achieved our goal of running open source AXI-based system verification, we are now working towards open source AXI verification in the MCU. While the Caliptra Subsystem Hardware Specification is still evolving, a key feature of note is the AXI command buffer that initiates transactions on the SoC for handling communications with Caliptra as well as taking responsibility for loading firmware onto other peripherals connected to the SoC.

By introducing open source testing for AXI via the UVM library into Verilator, the Caliptra project members will be able to benefit from a single standardized and open source verification flow as we work towards the release of Caliptra 2.0.

Antmicro’s improvements in Verilator

To create the single verification flow, we built on our previous work with Verilator, with several of those contributions being particularly essential in getting axi-vip to work with Verilator. Below, you can find some of the most important contributions to date:

• #5160 relates to supporting inout clocking items, which allow to both drive a clocked signal and read it without risking race conditions.
• #5235 added support for accessing clocking blocks in virtual interfaces. Clocking blocks allow avoiding races by being evaluated and executed in separate stages of a Verilog time slot. They are a recent feature in Verilator and this PR, together with PRs #5160, #5184 and #5430, provide more mature support. This helps with the creation of abstract synchronous models when used with virtual interfaces.
• #5273 introduced rand_mode, which allows users to disable randomization for a given class member.
• #5317 offers inline random variable control, letting users choose which class members they want to randomize at the call site.
• Other notable PRs relating to support for constrained randomization include those implementing foreach constraints #5302, conditional constraints #5245 and randomize() with #5234.

A wealth of other bugfixes were also contributed to Verilator in the context of axi-vip, including:

• Fix for stringification in nested preprocessor macro calls, as UVM makes heavy use of macros.
• Fix for the incorrect resolution of hierarchical symbols (symbols with dots, like a.b.c) in some cases,
• Fix for setting one-past-end element of a queue. In SystemVerilog, this appends an element to the queue, while in Verilator, it silently did nothing.
• A change that ensures that a signal reacts to changes in the corresponding clockvar in the Reactive region during the same clocking event.

axi-vip in Antimicro’s CI-based Verilator verification test suite

Consequently, Antmicro’s Verilator verification test suite has been expanded with support for axi-vip. The test suite checks verification features in Verilator such as concurrent assertions, functional coverage, randomization constraints and more. The suite runs in a CI system that produces useful dashboard-style output with the latest test report that becomes instantly available on GitHub. The individual test result for axi-vip is included here and shown below.

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO :   26
UVM_WARNING :  116
UVM_ERROR :    0
UVM_FATAL :    0
** Report counts by id
[AXI_WRAP_SQ]     3
[NO_DPI_TSTNAME]     1
[RNTST]     1
[UVM/COMP/NAME]   107
[UVM/COMP/NAMECHECK]     1
[UVM/DEPRECATED/COMP/OVM_PHASES]     8
[UVM/RELNOTES]     1
[UVM_TEST_TOP]     5
[UVM_TEST_TOP.AXI_E.AXIM_AGT.AXI_MON]     3
[UVM_TEST_TOP.AXI_E.AXIS_AGT.AXI_DRV]     1
[UVM_TEST_TOP.AXI_E.AXIS_AGT.AXI_MON]     3
[WRAP_PDR]     4
[WRAP_SB]     3
[uvm_sequence_base]     1

- /home/runner/work/verilator-verification-features-tests/verilator-verification-features-tests/uvm/src/base/uvm_root.svh:585: Verilog $finish

Test PASSED

- S i m u l a t i o n   R e p o r t: Verilator 5.029 devel
- Verilator: $finish at 26us; walltime 0.039 s; speed 1.264 ms/s
- Verilator: cpu 0.021 s on 1 threads; alloced 61 MB

To run the test independently from the rest of the verification suite, first clone the axi-vip test.

Next, set UVM_ROOT to the directory that contains the right version of UVM (included as a submodule in that repository; otherwise you can clone this). Make sure Verilator is in your PATH, along with a compatible solver like Z3 or CVC4.

Then run make.

Open source verification for your ASIC designs

As part of our work for customers, we work with and enhance tools such as Verilator or cocotb for creating transparent, reproducible and infinitely scalable workflows, supporting innovative ASIC applications for AI, Data Center and industrial use cases. To find out more, get in touch at contact@antmicro.com.