OPEN SIMULATION, OPEN SOURCE TOOLS
OPEN SIMULATION, OPEN SOURCE TOOLS

RUNNING LINUX AND ZEPHYR ON THE RENESAS RZ/G2L MPU IN RENODE

Published:

Linux and Zephyr on RZ/G2L

One of Renode’s practical advantages for real-world systems is its ability to simulate heterogeneous multi-core systems, such as ones including both Cortex-A and Cortex-M cores.

A recent example of an interesting platform of this kind that was added to...

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

IMPLEMENTING AUTOMATIC CLOCK GATING IN THE OPENROAD ASIC DESIGN TOOLCHAIN

Published:

Clock gating animation

Reducing power usage is a major aspect of chip design, important especially for energy-efficient systems and battery-powered devices. A significant amount of the power used by a typical chip is consumed by gate switching, and sequential logic (i.e. logic...

OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN SIMULATION
OPEN SOURCE TOOLS, OPEN HARDWARE, OPEN SIMULATION

RECENT IMPROVEMENTS TO ANTMICRO'S SIGNAL INTEGRITY SIMULATION FLOW: ADAPTIVE GRID GENERATION, DIFFERENTIAL PAIR SIMULATION AND MORE

Published:

SI simulation animation

Electromagnetic field simulation provides critical data on signal integrity, allowing for iterative design improvements before manufacturing and improved efficiency and reliability when developing dense designs with high-speed interfaces such PCIe Gen 5...

OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN ASICS, OPEN FPGA

POWER ESTIMATION IN OPENROAD USING SAIF IN VERILATOR

Published:

Power estimation with Verilator and OpenROAD

Power consumption is a major aspect of chip design, and the ability to reliably and efficiently predict it can save a lot of engineering cycles. While it is difficult to predict the exact consumption upfront without delving into the physical aspects of...

OLDER NEWER
CLOSE 

TAGS