Published:
Although cache modeling is usually not part of ISS level simulation, there are cases where it’s crucial to understand memory access patterns e.g., when building a new chip and deciding on cache size and layout, or working on low-level, time-critical firmware...
Published:
Real time applications such as space or automotive where instant autonomous decision making is crucial require configurable standardized interrupt controllers. There are many well-known examples such as the Global Interrupt Controller (GIC) for Cortex-A...
Published:
Debugging and extending ASIC and FPGA tools such as RTL simulators often means digging through vast codebases of not only the tooling itself but the designs they take as input. This can be cumbersome, especially in the context of very large, state-of-the...
Published:
Most of Verification IP, or VIP for short, used for industry-grade verification of state-of-the-art ASICs, depends on Unified Verification Methodology (UVM). The UVM library in turn, though itself open source, makes use of nearly every imaginable feature...
Published:
In recent years Antmicro has been working for customers within the CHIPS Alliance’s Caliptra Workgroup, led by AMD, Google, Microsoft and NVIDIA, to maintain and gradually enhance the RISC-V VeeR EL2 CPU core that is used in the open source Caliptra Root...
Published:
Asymmetric multiprocessing (AMP) setups are very common in modern SoCs which mix various types of cores or even architectures to provide sufficient processing power when needed, while keeping the system energy efficient overall. The AMP architecture is...
