OPEN FPGA, OPEN ASICS
OPEN FPGA, OPEN ASICS

DYNAMIC SCHEDULING IN VERILATOR - MILESTONE TOWARDS OPEN SOURCE UVM

Published:

Dynamic scheduling in Verilator

UVM is a verification methodology traditionally used in chip design which has historically been missing from the open source landscape of verification-focused tooling. While new, open source approaches to verification have emerged that include the excellent...

OPEN HARDWARE, OPEN ISA, OPEN MACHINE VISION, EDGE AI
OPEN HARDWARE, OPEN ISA, OPEN MACHINE VISION

RUN LINUX ON BEAGLEV STARLIGHT IN RENODE

Published:

Beagle-V Starlight drawing

BeagleV Starlight is an upcoming affordable general-purpose Linux-capable RISC-V platform, and as such understandably generates a lot of interest in the development community. It is currently in beta stage and limited supply, so we thought it’s a great...

OPEN ISA, OPEN ASICS
OPEN ISA, OPEN ASICS

ANTMICRO’S ARVSOM RISC-V MODULE ANNOUNCED

Published:

ARVSOM

We are excited to announce the ARVSOM - Antmicro’s fully open source, RISC-V-based system-on-module featuring the StarFive 71x0 SoC. Using the RISC-V architecture, which Antmicro has been heavily involved in since the early days as a Founding Member of...

OPEN ISA, EDGE AI, OPEN SOURCE TOOLS, OPEN HARDWARE
OPEN ISA, EDGE AI, OPEN SOURCE TOOLS

RENODE 1.12 RELEASE - NEW PLATFORMS, SENSORS AND DEBUGGING FEATURES

Published:

RE 1.12

Originally created to meet Antmicro’s internal need for a flexible system design and testing tool, Renode has been in use by numerous projects and organizations including internet giants like Google, Microsoft and Amazon, semiconductors like Arm, Intel...

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