OPEN ASICS, OPEN HARDWARE, OPEN ISA
OPEN ASICS, OPEN HARDWARE, OPEN ISA

PRESS RELEASE: ANTMICRO AND ZGLUE RELEASE RAPID TURNAROUND CHIPLET-BASED GEM ASIC

Published:

GEM1

SAN JOSE, CA – December 10th, 2019 – Today, edge AI technology expert company and RISC-V leader Antmicro, and zGlue, a Silicon Valley startup democratizing the procedure of custom chip creation using their innovative chiplet technology, have announced...

OPEN SOURCE TOOLS, OPEN OS, EDGE AI, OPEN FPGA
OPEN SOURCE TOOLS, OPEN OS, EDGE AI

TENSORFLOW LITE IN ZEPHYR ON LITEX/VEXRISCV

Published:

TensorFlow Lite and Zephyr logos

While much of the focus for the recent developments in AI has been on cloud-centric implementations, there are many use cases where AI algorithms have to be run on small and resource constrained devices. Google’s TensorFlow Lite, a smaller brother of one...

OPEN FPGA, OPEN SOURCE TOOLS
OPEN FPGA, OPEN SOURCE TOOLS

TESTING OPEN SOURCE USB IP CORES WITH PYTHON AND COCOTB

Published:

USB testing diagram

USB is often a daunting topic for developers, and implementing support for it from scratch is a time consuming task. When the expected result is more complicated than a USB-to-serial bridge, the solution would be to either use a hardware transceiver or...

OPEN FPGA, OPEN SOURCE TOOLS, OPEN ASICS
OPEN FPGA, OPEN SOURCE TOOLS, OPEN ASICS

AN OPEN SOURCE SYSTEMVERILOG TEST SUITE

Published:

SystemVerilog logo

At Antmicro, we work with improving development flows for both software, hardware, FPGA and ASIC design, for which we use, contribute to and produce a wide variety of open source tools.

Verilog, SystemVerilog and open tooling

For FPGA development flows...

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