OPEN SOURCE TOOLS, OPEN FPGA
OPEN SOURCE TOOLS, OPEN FPGA

CO-SIMULATING HDL MODELS IN RENODE WITH VERILATOR

Published:

Renode - Verilator UARTLite co-simulation demo

Antmicro’s open source simulation framework, Renode, was built to enable simulating real-life scenarios - which have a tendency to be complex and require hybrid approaches.

That’s why, besides other things, the Renode 1.7.1 release has introduced an integration...

OPEN OS
OPEN OS

ZEPHYR RTOS AND CORTEX-R5 ON ZYNQ ULTRASCALE+

Published:

X-Mine

The UltraScale+, a high-performance FPGA SoC designed for heterogeneous processing with 4 Cortex-A53 cores and 2 Cortex-R5 cores, is often used in Antmicro’s projects. For certain complex devices, the combined processing capabilities of the US+ FPGA SoC...

OPEN SOURCE TOOLS
OPEN SOURCE TOOLS

MULTI-CORE DEBUGGING WITH GDB IN RENODE

Published:

Multi-core debugging with GDB

Antmicro‘s open source simulation framework, Renode, provides a familiar debugging experience to embedded development teams by serving as a target for remote GDB connections, which allows users to work with GDB or GDB-based IDEs as they normally would with...

ANTMICRO TO PARTICIPATE IN INAUGURAL CHIPS ALLIANCE WORKSHOP

Published:

Antmicro at CHIPS Alliance Workshop

The inaugural CHIPS Alliance Workshop, due to start tomorrow, June 19th, 2019 at Google’s Sunnyvale campus, CA, will see member companies Antmicro, Esperanto, Google, SiFive and Western Digital welcoming industry stakeholders and developers for an introduction...

OLDER NEWER
CLOSE 

TAGS