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Open source toolchains are key to building collaborative ecosystems, welcoming to new approaches, opportunistic/focused innovations and niche use cases. The ASIC design domain, especially in the view of the rising tensions...
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With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter is a static code analysis tool that has been helping...
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Open source hardware is undeniably undergoing a renaissance whose origin can be traced to the establishment of RISC-V Foundation (later redubbed RISC-V International). The open ISA and ecosystem, in which Antmicro participated...
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Antmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine various solutions, unlocking system...
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Throughout 2020 we have been hard at work developing proper, portable SystemVerilog support for multiple open-source FPGA and ASIC design tools used by us and our customers, most notably Yosys and Verilator. We strongly believe...
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While developing FPGA designs it is important to keep track of resource usage and runtime to make sure that your development process is productive and your FPGA hardware delivers the best possible results. This is where one...
